LM3S9U92_15 Datasheet, PDF (1280/1412 Pages) Texas Instruments – Stellaris LM3S9U92 Microcontroller

Signal Tables
Table 24-7. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
PH4
I/O
TTL
GPIO port H bit 4.
EPI0S10
B10
SSI1Clk
I/O
TTL
EPI module 0 signal 10.
I/O
TTL
SSI module 1 clock.
USB0PFLT
I
TTL
Optionally used in Host mode by an external power source to
indicate an error state by that power source.
PE0
I/O
TTL
GPIO port E bit 0.
CCP3
I/O
TTL
Capture/Compare/PWM 3.
EPI0S8
I/O
TTL
EPI module 0 signal 8.
B11
PWM4
O
TTL
PWM 4. This signal is controlled by PWM Generator 2.
SSI1Clk
I/O
TTL
SSI module 1 clock.
USB0PFLT
I
TTL
Optionally used in Host mode by an external power source to
indicate an error state by that power source.
B12
USB0RBIAS
O
Analog 9.1-kΩ resistor (1% precision) used internally for USB analog
circuitry.
C1
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
C2
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
VDDC
C3
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals. The voltage on this pin is
1.3 V and is supplied by the on-chip LDO. The VDDC pins should
only be connected to the LDO pin and an external capacitor as
specified in Table 26-6 on page 1322 .
C4
GND
-
Power Ground reference for logic and I/O pins.
C5
GND
-
Power Ground reference for logic and I/O pins.
PD5
I/O
TTL
GPIO port D bit 5.
AIN6
I
Analog Analog-to-digital converter input 6.
CCP2
I/O
TTL
Capture/Compare/PWM 2.
C6
CCP4
I/O
TTL
Capture/Compare/PWM 4.
EPI0S28
I/O
TTL
EPI module 0 signal 28.
I2S0RXMCLK
I/O
TTL
I²S module 0 receive master clock.
U2Rx
I
TTL
UART module 2 receive. When in IrDA mode, this signal has IrDA
modulation.
VDDA
C7
-
Power The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be supplied with a voltage that meets
the specification in Table 26-2 on page 1317 , regardless of system
implementation.
PH1
I/O
TTL
GPIO port H bit 1.
CCP7
I/O
TTL
Capture/Compare/PWM 7.
C8
EPI0S7
I/O
TTL
EPI module 0 signal 7.
PWM3
O
TTL
PWM 3. This signal is controlled by PWM Generator 1.
PWM5
O
TTL
PWM 5. This signal is controlled by PWM Generator 2.
1280
Texas Instruments-Production Data
July 03, 2014