OMAP-L132 Datasheet, PDF (13/227 Pages) Texas Instruments – OMAP-L132 C6-Integra DSP+ARM Processor

OMAP-L132
www.ti.com
SPRS762 – AUGUST 2011
2.4.2 DSP Memory Mapping
The DSP memory map is shown in Section 2.5.
By default the DSP also has access to most on and off chip memory areas.
Additionally, the DSP megamodule includes the capability to limit access to its internal memories through
its SDMA port; without needing an external MPU unit.
2.4.2.1 ARM Internal Memories
The DSP does not have access to the ARM internal memory.
2.4.2.2 External Memories
The DSP has access to the following External memories:
• Asynchronous EMIF / SDRAM / NAND / NOR Flash (EMIFA)
• SDRAM (DDR2)
2.4.2.3 DSP Internal Memories
The DSP has access to the following DSP memories:
• L2 RAM
• L1P RAM
• L1D RAM
2.4.2.4 C674x CPU
The C674x core uses a two-level cache-based architecture. The Level 1 Program cache (L1P) is 32 KB
direct mapped cache and the Level 1 Data cache (L1D) is 32 KB 2-way set associated cache. The Level 2
memory/cache (L2) consists of a 256 KB memory space that is shared between program and data space.
L2 memory can be configured as mapped memory, cache, or a combination of both.
Table 2-2 shows a memory map of the C674x CPU cache registers for the device.
Byte Address
0x0184 0000
0x0184 0020
0x0184 0024
0x0184 0040
0x0184 0044
0x0184 0048 - 0x0184 0FFC
0x0184 1000
0x0184 1004 - 0x0184 1FFC
0x0184 2000
0x0184 2004
0x0184 2008
0x0184 200C
0x0184 2010 - 0x0184 3FFF
0x0184 4000
0x0184 4004
0x0184 4010
0x0184 4014
0x0184 4018
0x0184 401C
Table 2-2. C674x Cache Registers
Register Name
L2CFG
L1PCFG
L1PCC
L1DCFG
L1DCC
-
EDMAWEIGHT
-
L2ALLOC0
L2ALLOC1
L2ALLOC2
L2ALLOC3
-
L2WBAR
L2WWC
L2WIBAR
L2WIWC
L2IBAR
L2IWC
Register Description
L2 Cache configuration register
L1P Size Cache configuration register
L1P Freeze Mode Cache configuration register
L1D Size Cache configuration register
L1D Freeze Mode Cache configuration register
Reserved
L2 EDMA access control register
Reserved
L2 allocation register 0
L2 allocation register 1
L2 allocation register 2
L2 allocation register 3
Reserved
L2 writeback base address register
L2 writeback word count register
L2 writeback invalidate base address register
L2 writeback invalidate word count register
L2 invalidate base address register
L2 invalidate word count register
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