OMAP-L132 Datasheet, PDF (1/227 Pages) Texas Instruments – OMAP-L132 C6-Integra DSP+ARM Processor

OMAP-L132
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OMAP-L132 C6-Integra™ DSP+ARM® Processor
Check for Samples: OMAP-L132
SPRS762 – AUGUST 2011
1 OMAP-L132 C6-Integra™ DSP+ARM® Processor
1.1 Features
12
• Highlights
– Dual Core SoC
• 200-MHz ARM926EJ-S™ RISC MPU
• 200-MHz C674x Fixed/Floating-Point VLIW
DSP
– Supports TI’s Basic Secure Boot
– Enhanced Direct-Memory-Access Controller
(EDMA3)
– DDR2/Mobile DDR Memory Controller
– Two Multimedia Card (MMC)/Secure Digital
(SD) Card Interface
– 10/100 Mb/s Ethernet MAC (EMAC)
– Programmable Real-Time Unit Subsystem
– Three Configurable UART Modules
– One Multichannel Audio Serial Port
– Two Multichannel Buffered Serial Ports
• Dual Core SoC
– 200-MHz ARM926EJ-S™ RISC MPU
– 200-MHz C674x Fixed/Floating-Point VLIW
DSP
• ARM926EJ-S Core
– 32-Bit and 16-Bit (Thumb®) Instructions
– DSP Instruction Extensions
– Single Cycle MAC
– ARM® Jazelle® Technology
– EmbeddedICE-RT™ for Real-Time Debug
• ARM9 Memory Architecture
– 16K-Byte Instruction Cache
– 16K-Byte Data Cache
– 8K-Byte RAM (Vector Table)
– 64K-Byte ROM
• C674x™ Instruction Set Features
– Superset of the C67x+™ and C64x+™ ISAs
– Up to 1600/1200 C674x MIPS/MFLOPS
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– 8-Bit Overflow Protection
– Bit-Field Extract, Set, Clear
– Normalization, Saturation, Bit-Counting
– Compact 16-Bit Instructions
• C674x Two Level Cache Memory Architecture
– 32K-Byte L1P Program RAM/Cache
– 32K-Byte L1D Data RAM/Cache
– 256K-Byte L2 Unified Mapped RAM/Cache
– Flexible RAM/Cache Partition (L1 and L2)
• Enhanced Direct-Memory-Access Controller 3
(EDMA3):
– 2 Channel Controllers
– 3 Transfer Controllers
– 64 Independent DMA Channels
– 16 Quick DMA Channels
– Programmable Transfer Burst Size
• TMS320C674x Floating-Point VLIW DSP Core
– Load-Store Architecture With Non-Aligned
Support
– 64 General-Purpose Registers (32 Bit)
– Six ALU (32-/40-Bit) Functional Units
• Supports 32-Bit Integer, SP (IEEE Single
Precision/32-Bit) and DP (IEEE Double
Precision/64-Bit) Floating Point
• Supports up to Four SP Additions Per
Clock, Four DP Additions Every 2 Clocks
• Supports up to Two Floating Point (SP or
DP) Reciprocal Approximation (RCPxP)
and Square-Root Reciprocal
Approximation (RSQRxP) Operations Per
Cycle
– Two Multiply Functional Units
• Mixed-Precision IEEE Floating Point
Multiply Supported up to:
– 2 SP x SP → SP Per Clock
– 2 SP x SP → DP Every Two Clocks
– 2 SP x DP → DP Every Three Clocks
– 2 DP x DP → DP Every Four Clocks
• Fixed Point Multiply Supports Two 32 x
32-Bit Multiplies, Four 16 x 16-Bit
Multiplies, or Eight 8 x 8-Bit Multiplies per
Clock Cycle, and Complex Multiples
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– Hardware Support for Modulo Loop
Operation
– Protected Mode Operation
– Exceptions Support for Error Detection and
Program Redirection
1
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2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated