LM3S5D51 Datasheet, PDF (13/1266 Pages) Texas Instruments – Stellaris® LM3S5D51 Microcontroller

Stellaris^® LM3S5D51 Microcontroller
Figure 17-2. CAN Data/Remote Frame .................................................................................. 815
Figure 17-3. Message Objects in a FIFO Buffer ...................................................................... 823
Figure 17-4. CAN Bit Time .................................................................................................... 827
Figure 18-1. USB Module Block Diagram ............................................................................... 864
Figure 19-1. Analog Comparator Module Block Diagram ....................................................... 1002
Figure 19-2. Structure of Comparator Unit ............................................................................ 1004
Figure 19-3. Comparator Internal Reference Structure .......................................................... 1005
Figure 20-1. PWM Module Diagram ..................................................................................... 1017
Figure 20-2. PWM Generator Block Diagram ........................................................................ 1017
Figure 20-3. PWM Count-Down Mode .................................................................................. 1021
Figure 20-4. PWM Count-Up/Down Mode ............................................................................. 1022
Figure 20-5. PWM Generation Example In Count-Up/Down Mode .......................................... 1022
Figure 20-6. PWM Dead-Band Generator ............................................................................. 1023
Figure 21-1. QEI Block Diagram .......................................................................................... 1089
Figure 21-2. Quadrature Encoder and Velocity Predivider Operation ...................................... 1092
Figure 22-1. 100-Pin LQFP Package Pin Diagram ................................................................ 1111
Figure 22-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................. 1112
Figure 25-1. Load Conditions ............................................................................................... 1187
Figure 25-2. JTAG Test Clock Input Timing ........................................................................... 1188
Figure 25-3. JTAG Test Access Port (TAP) Timing ................................................................ 1188
Figure 25-4. Power-On Reset Timing ................................................................................... 1189
Figure 25-5. Brown-Out Reset Timing .................................................................................. 1189
Figure 25-6. Power-On Reset and Voltage Parameters ......................................................... 1190
Figure 25-7. External Reset Timing (RST) ............................................................................ 1190
Figure 25-8. Software Reset Timing ..................................................................................... 1190
Figure 25-9. Watchdog Reset Timing ................................................................................... 1191
Figure 25-10. MOSC Failure Reset Timing ............................................................................. 1191
Figure 25-11. Hibernation Module Timing with Internal Oscillator Running in Hibernation .......... 1196
Figure 25-12. Hibernation Module Timing with Internal Oscillator Stopped in Hibernation .......... 1196
Figure 25-13. ADC Input Equivalency Diagram ....................................................................... 1198
Figure 25-14. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................. 1199
Figure 25-15. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............... 1200
Figure 25-16. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................... 1200
Figure 25-17. I²C Timing ....................................................................................................... 1201
Figure 25-18. I²S Master Mode Transmit Timing ..................................................................... 1202
Figure 25-19. I²S Master Mode Receive Timing ...................................................................... 1202
Figure 25-20. I²S Slave Mode Transmit Timing ....................................................................... 1203
Figure 25-21. I²S Slave Mode Receive Timing ........................................................................ 1203
Figure C-1. Stellaris LM3S5D51 100-Pin LQFP Package Dimensions ................................... 1257
Figure C-2. 100-Pin LQFP Tray Dimensions ........................................................................ 1259
Figure C-3. 100-Pin LQFP Tape and Reel Dimensions ......................................................... 1260
Figure C-4. Stellaris LM3S5D51 108-Ball BGA Package Dimensions .................................... 1261
Figure C-5. 108-Ball BGA Tray Dimensions ......................................................................... 1263
Figure C-6. 108-Ball BGA Tape and Reel Dimensions .......................................................... 1264
January 23, 2012
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Texas Instruments-Production Data