LM3S5D51 Datasheet, PDF (12/1266 Pages) Texas Instruments – Stellaris® LM3S5D51 Microcontroller

Table of Contents
Figure 12-7. ADC Input Equivalency Diagram ......................................................................... 559
Figure 12-8. Internal Voltage Conversion Result ..................................................................... 560
Figure 12-9. External Voltage Conversion Result with 3.0-V Setting ......................................... 561
Figure 12-10. External Voltage Conversion Result with 1.0-V Setting ......................................... 561
Figure 12-11. Differential Sampling Range, V_{IN_ODD} = 1.5 V ...................................................... 563
Figure 12-12. Differential Sampling Range, V_{IN_ODD} = 0.75 V .................................................... 563
Figure 12-13. Differential Sampling Range, V_{IN_ODD} = 2.25 V .................................................... 564
Figure 12-14. Internal Temperature Sensor Characteristic ......................................................... 565
Figure 12-15. Low-Band Operation (CIC=0x0 and/or CTC=0x0) ................................................ 567
Figure 12-16. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ................................................. 568
Figure 12-17. High-Band Operation (CIC=0x3 and/or CTC=0x3) ................................................ 569
Figure 13-1. UART Module Block Diagram ............................................................................. 632
Figure 13-2. UART Character Frame ..................................................................................... 635
Figure 13-3. IrDA Data Modulation ......................................................................................... 637
Figure 13-4. LIN Message ..................................................................................................... 639
Figure 13-5. LIN Synchronization Field ................................................................................... 640
Figure 14-1. SSI Module Block Diagram ................................................................................. 696
Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 700
Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 700
Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 701
Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 701
Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 702
Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 703
Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 703
Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 704
Figure 14-10. MICROWIRE Frame Format (Single Frame) ........................................................ 705
Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 706
Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 706
Figure 15-1. I²C Block Diagram ............................................................................................. 738
Figure 15-2. I²C Bus Configuration ........................................................................................ 739
Figure 15-3. START and STOP Conditions ............................................................................. 740
Figure 15-4. Complete Data Transfer with a 7-Bit Address ....................................................... 740
Figure 15-5. R/S Bit in First Byte ............................................................................................ 741
Figure 15-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 741
Figure 15-7. Master Single TRANSMIT .................................................................................. 745
Figure 15-8. Master Single RECEIVE ..................................................................................... 746
Figure 15-9. Master TRANSMIT with Repeated START ........................................................... 747
Figure 15-10. Master RECEIVE with Repeated START ............................................................. 748
Figure 15-11. Master RECEIVE with Repeated START after TRANSMIT with Repeated
START .............................................................................................................. 749
Figure 15-12. Master TRANSMIT with Repeated START after RECEIVE with Repeated
START .............................................................................................................. 750
Figure 15-13. Slave Command Sequence ................................................................................ 751
Figure 16-1. I²S Block Diagram ............................................................................................. 776
Figure 16-2. I²S Data Transfer ............................................................................................... 779
Figure 16-3. Left-Justified Data Transfer ................................................................................ 779
Figure 16-4. Right-Justified Data Transfer .............................................................................. 779
Figure 17-1. CAN Controller Block Diagram ............................................................................ 813
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January 23, 2012
Texas Instruments-Production Data