BQ2022_13 Datasheet, PDF (13/20 Pages) Texas Instruments – 1K-BIT SERIAL EPROM WITH SDQ INTERFACE

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bq2022
SLUS526F – OCTOBER 2002 – REVISED DECEMBER 2006
From ROM
Command
Program
N
Profile Command?
99h
Y
bq2022 Transmits
55h
Other
Command
Codes
Master Issues Reset
bq2022 is in
Reset State
Figure 12. PROGRAM PROFILE Command Flow
UDG-02067
SDQ Signaling
All SDQ signaling begins with initializing the device, followed by the host driving the bus low to write a 1 or 0, or
to begin the start frame for a bit read. Figure 13 shows the initialization timing, whereas Figure 14 and Figure 15
show that the host initiates each bit by driving the DATA bus low for the start period, t_WSTRB / t_RSTRB. After the bit
is initiated, either the host continues controlling the bus during a WRITE, or the bq2022 responds during a
READ.
RESET AND PRESENCE PULSE
If the DATA bus is driven low for more than 120 µs, the bq2022 may be reset. Figure 13 shows that if the DATA
bus is driven low for more than 480 µs, the bq2022 resets and indicates that it is ready by responding with a
PRESENCE PULSE.
V_PU
V_IH
V_IL
RESET
(Sent by Host)
t_RST
Presence Pulse
(Sent by bq2022)
t_PPD
t_PP
t_RSTREC
Figure 13. Reset Timing Diagram
UDG-02067
WRITE
The WRITE bit timing diagram in Figure 14 shows that the host initiates the transmission by issuing the t_WSTRB
portion of the bit and then either driving the DATA bus low for a WRITE 0, or releasing the DATA bus for a
WRITE 1.
VPU _VIH
V _IL
Write ”1”
Write ”0”
t _WSTRB
t _WDSU
t _WDH
t _rec
Figure 14. Write Bit Timing Diagram
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