BQ2022_13 Datasheet, PDF (12/20 Pages) Texas Instruments – 1K-BIT SERIAL EPROM WITH SDQ INTERFACE

bq2022
SLUS526F – OCTOBER 2002 – REVISED DECEMBER 2006
www.ti.com
programmed byte. If the programmed byte is incorrect, then the host must reset the device and begin the write
sequence again. If the bq2022 EPROM data byte programming was successful, the bq2022 automatically
increments its address counter to select the next byte in the STATUS MEMORY data field. The least significant
byte of the new two-byte address is also loaded into the 8-bit CRC generator as a starting value. The host
issues the next byte of data using eight write time slots.
As the bq2022 receives this byte of data into the RAM buffer, it also shifts the data into the CRC generator that
has been preloaded with the LSB of the current address and the result is an 8-bit CRC of the new data byte and
the LSB of the new address. After supplying the data byte, the host reads this 8-bit CRC from the bq2022 with
eight read time slots to confirm that the address incremented properly and the data byte was received correctly.
If the CRC is incorrect, a Reset Pulse must be issued and the Write Status command sequence must be
restarted. If the CRC is correct, the host issues a programming pulse and the selected byte in memory is
programmed.
NOTE:
The initial write of the WRITE STATUS command, generates an 8-bit CRC value that
is the result of shifting the command byte into the CRC generator, followed by the
two-address bytes, and finally the data byte. Subsequent writes within this WRITE
STATUS command due to the bq2022 automatically incrementing its address counter
generates an 8-bit CRC that is the result of loading (not shifting) the LSB of the new
(incremented) address into the CRC generator and then shifting in the new data byte.
For both of these cases, the decision to continue programming the EPROM Status registers is made entirely by
the host, because the bq2022 is not able to determine if the 8-bit CRC calculated by the host agrees with the
8-bit CRC calculated by the bq2022. If an incorrect CRC is ignored and a program pulse is applied by the host,
incorrect programming could occur within the bq2022. Also note that the bq2022 always increments its internal
address counter after the receipt of the eight read time slots used to confirm the programming of the selected
EPROM byte. The decision to continue is again made entirely by the host, therefore if the EPROM data byte
does not match the supplied data byte but the master continues with the WRITE STATUS command, incorrect
programming could occur within the bq2022. The WRITE STATUS command sequence can be ended at any
point by issuing a reset pulse.
Table 3. Command Code Summary
COMMAND
(HEX)
33h
55h
F0h
CCh
F0h
AAh
C3h
0Fh
99h
55h
DESCRIPTION
Read Serialization ROM and
CRC
Match Serialization ROM
Search Serialization ROM
Skip Serialization ROM
Read Memory/Field CRC
Read EPROM Status
Read Memory/Page CRC
Write Memory
Programming Profile
Write EPROM Status
5Ah
Program Control
CATEGORY
ROM Commands Available in Command Level I
Memory Function Commands
Available in Command Level II
Program Command Available Only in WRITE
MEMORY and WRITE STATUS Modes
PROGRAM PROFILE BYTE
The PROGRAM PROFILE byte is read to determine the WRITE MEMORY programming sequence required by
a specific manufacturer. After issuing a ROM command, the host issues the PROGRAM PROFILE BYTE
command, 99h. Figure 12 shows the the bq2022 responds with 55h. This informs the host that the WRITE
MEMORY programming sequence is the one described in the WRITE MEMORY command section of this data
sheet.
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