TMS320C6654_15 Datasheet, PDF (129/235 Pages) Texas Instruments – Fixed and Floating-Point Digital Signal Processor

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TMS320C6654
SPRS841B – MARCH 2012 – REVISED APRIL 2015
8.5 Main PLL and PLL Controller
This section provides a description of the Main PLL and the PLL controller. For details on the operation of
the PLL controller module, see the Phase Locked Loop (PLL) for KeyStone Devices User's Guide
(SPRUGV2).
The Main PLL is controlled by the standard PLL controller. The PLL controller manages the clock ratios,
alignment, and gating for the system clocks to the device. Figure 8-7 shows a block diagram of the main
PLL and the PLL controller.
CORECLK(N|P)
PLL
PLLD xPLLM /2
0
OUTPUT
DIVIDE
1
BYPASS
PLLOUT
PLL Controller
1
0
01
PLLEN 0
PLLENSRC
/1
PLLDIV1
/x
PLLDIV2
/2
PLLDIV3
/3
PLLDIV4
/y
PLLDIV5
/64
PLLDIV6
/6
PLLDIV7
/z
PLLDIV8
/12
PLLDIV9
/3
PLLDIV10
/6
PLLDIV11
SYSCLK1
SYSCLK2
C66x
CorePac
SYSCLK3
SYSCLK4
SYSCLK5
SYSCLK6
SYSCLK7
To Switch Fabric,
Peripherals,
Accelerators
SYSCLK8
SYSCLK9
SYSCLK10
SYSCLK11
Figure 8-7. Main PLL and PLL Controller
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Peripheral Information and Electrical Specifications 129
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