TMS320C6654_15 Datasheet, PDF (108/235 Pages) Texas Instruments – Fixed and Floating-Point Digital Signal Processor

TMS320C6654
SPRS841B – MARCH 2012 – REVISED APRIL 2015
www.ti.com
7.2 Recommended Operating Conditions⁽¹⁾⁽²⁾
CVDD
CVDD1
DVDD18
DVDD15
VREFSSTL
V_DDRx ⁽⁵⁾
V_DDAx
V_DDTx
V_SS
V_IH
V_IL
T_C
SR Core Supply
850MHz - Device
Core supply voltage for memory array
1.8-V supply I/O voltage
1.5-V supply I/O voltage
DDR3 reference voltage
SerDes regulator supply
PLL analog supply
SerDes termination supply
Ground
High-level input voltage
LVCMOS (1.8 V)
I²C
DDR3 EMIF
LVCMOS (1.8 V)
Low-level input voltage
DDR3 EMIF
I²C
Operating case
temperature
Commercial
Extended
MIN
SRVnom⁽³⁾ × 0.95
0.95
1.71
1.425
0.49 × DVDD15
1.425
1.71
0.95
0
0.65 × DVDD18
0.7 × DVDD18
VREFSSTL + 0.1
-0.3
0
-40
NOM
0.85-1.1 ⁽⁴⁾
1
1.8
1.5
0.5 × DVDD15
1.5
1.8
1
0
MAX
SRVnom × 1.05
1.05
1.89
1.575
0.51 × DVDD15
1.575
1.89
1.05
0
0.35 × DVDD18
VREFSSTL - 0.1
0.3 × DVDD18
85
100
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
(1) All differential clock inputs comply with the LVDS Electrical Specification, IEEE 1596.3-1996 and all SERDES I/Os comply with the XAUI
Electrical Specification, IEEE 802.3ae-2002.
(2) All SERDES I/Os comply with the XAUI Electrical Specification, IEEE 802.3ae-2002.
(3) SRVnom refers to the unique SmartReflex core supply voltage set from the factory for each individual device.
(4) The initial CVDD voltage at power on will be 1.1V nominal and it must transition to VID set value immediately after being presented on
VCNTL pins. This is required to maintain full power functionality and reliability targets guaranteed by TI.
(5) Where x = 1, 2, 3, 4... to indicate all supplies of the same kind.
108 Device Operating Conditions
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