TMS320C6654_15 Datasheet, PDF (1/235 Pages) Texas Instruments – Fixed and Floating-Point Digital Signal Processor

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TMS320C6654
SPRS841B – MARCH 2012 – REVISED APRIL 2015
TMS320C6654 Fixed and Floating-Point Digital Signal Processor
1 C6654 Features and Description
1.1 Features
1
• One TMS320C66x™ DSP Core Subsystem
(CorePac) With
– 850 MHz C66x Fixed/Floating-Point CPU Core
• 27.2 GMAC/Core for Fixed Point @ 850 MHz
• 13.6 GFLOP/Core for Floating Point @ 850
MHz
– Memory
• 32K Byte L1P Per Core
• 32K Byte L1D Per Core
• 1024K Byte Local L2 Per Core
• Multicore Shared Memory Controller (MSMC)
– Memory Protection Unit for DDR3_EMIF
• Multicore Navigator
– 8192 Multipurpose Hardware Queues with
Queue Manager
– Packet-Based DMA for Zero-Overhead
Transfers
• Peripherals
– PCIe Gen2
• Single Port Supporting 1 or 2 Lanes
• Supports Up To 5 GBaud Per Lane
– Gigabit Ethernet (GbE) Subsystem
• One SGMII Port
• Supports 10/100/1000 Mbps Operation
– 32-Bit DDR3 Interface
• DDR3-1066
• 8G Byte Addressable Memory Space
– 16-Bit EMIF
– Universal Parallel Port
• Two Channels of 8 bits or 16 bits Each
• Supports SDR and DDR Transfers
– Two UART Interfaces
– Two Multichannel Buffered Serial Ports
(McBSP)
– I²C Interface
– 32 GPIO Pins
– SPI Interface
– Semaphore Module
– Eight 64-Bit Timers
– Two On-Chip PLLs
• Commercial Temperature:
– 0°C to 85°C
• Extended Temperature:
– - 40°C to 100°C
• Extended Low Temperature:
– - 55°C to 100°C
1.2 KeyStone Architecture
TI’s KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP
cores with application specific coprocessors and I/O. KeyStone is the first of its kind that provides
adequate internal bandwidth for nonblocking access to all processing cores, peripherals, coprocessors,
and I/O. This is achieved with four main hardware elements: Multicore Navigator, TeraNet, Multicore
Shared Memory Controller, and HyperLink.
Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are
allocated to the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to
the appropriate available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity
of the TeraNet switched central resource to move packets. The Multicore Shared Memory Controller
enables processing cores to access shared memory directly without drawing from TeraNet’s capacity, so
packet movement cannot be blocked by memory access.
HyperLink provides a 40-Gbaud chip-level interconnect that allows SoCs to work in tandem. Its low-
protocol overhead and high throughput make HyperLink an ideal interface for chip-to-chip
interconnections. Working with Multicore Navigator, HyperLink dispatches tasks to tandem devices
transparently and executes tasks as if they are running on local resources.
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.