THS1215_15 Datasheet, PDF (12/22 Pages) Texas Instruments – 3.3-V, 12-BIT, 15 MSPS, LOW-POWER ANALOG-TO-DIGITAL

THS1215
Not Recommended For New Designs
SLAS292A – MARCH 2001 – REVISED MARCH 2004
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Table 2 assumes that the delta in ADC reference voltages V_REFT and V_REFB is set to 1 V, i.e., V_REFT – V_REFB = 1
V. Note that V_REFB and V_REFT can be set externally, which will scale the numbers given in this table.
The user-chosen operating configuration and reference voltages determine what input signal voltage range the
THS1215 can handle.
The following sections explain both the internal signal flow of the device and how the input signal span is related
to the ADC reference voltages, as well as the ways in which the ADC reference voltages can be buffered
internally or externally applied.
SIGNAL PROCESSING CHAIN (Sample and Hold, ADC)
Figure 15 shows the signal flow through the sample and hold unit and the PGA to the ADC core.
REFT
AIN+
AIN−
+1
SAMPLE
−1 ^AND
HOLD
VP+
VP−
ADC
CORE
REFB
Figure 15. Analog Input Signal Flow
Sample and Hold
The differential sample and hold processes A_IN with respect to the voltages applied to the REFT and REFB pins,
to give a differential output (VP+) – (VP–) = VP given by:
• VP = (AIN+) – ( AIN–)
Analog-to-Digital Converter
No matter what operating configuration is chosen, VP is digitized against ADC reference voltages V_REFT and
V_REFB. The V_REFT and V_REFB voltages set the analog input span limits FS+ and FS–, respectively. Any voltages at
AIN greater than REFT or less than REFB causes ADC over-range, which is signaled by OVR going high when
the conversion result is output.
Analog input
A first-order approximation for the equivalent analog input circuit of the THS1215 is shown in Figure 16. The
equivalent input capacitance C_I is 5 pF typical. The input must charge/discharge this capacitance within the
sample period of one half of a clock cycle. When a full-scale voltage step is applied, the input source provides
the charging current through the switch resistance R_SW (200 Ω) of S1 and quickly settles. In this case the input
impedance is low. Alternatively, when the source voltage equals the value previously stored on C_I, the hold
capacitor requires no input current and the equivalent input impedance is high.
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