DS90CR215_15 Datasheet, PDF (12/23 Pages) Texas Instruments – +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 66 MHz

DS90CR215, DS90CR216
SNLS129D – MARCH 1999 – REVISED APRIL 2013
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C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and
max
Tppos—Transmitter output pulse position (min and max)
RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference)
Cable Skew—typicaIIy 10 ps–40 ps per foot, media dependent
Cycle-to-cycle jitter is less than 250 ps
ISI is dependent on interconnect length; may be zero
Figure 22. Receiver LVDS Input Skew Margin
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