ADS5263_15 Datasheet, PDF (12/84 Pages) Texas Instruments – Quad Channel 16-Bit, 100-MSPS High-SNR ADC

ADS5263
SLAS760D – MAY 2011 – REVISED NOVEMBER 2015
www.ti.com
7.8 Digital Characteristics
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1. AVDD = 3.3V, LVDD = 1.8V
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
DIGITAL INPUTS – RESET, SCLK, SDATA, CS, PDN, SYNC, INT/EXT
V_IH High-level input voltage
All digital inputs support 1.8-V and
3.3-V CMOS logic levels.
1.3
V
V_IL Low-level input voltage
I_IH
High-level input
current
SDATA, SCLK, CS ⁽¹⁾ V_HIGH = 1.8 V
0.4 V
5
μA
I_IL
Low-level input
current
SDATA, SCLK, CS V_LOW = 0 V
0
μA
DIGITAL CMOS OUTPUT – SDOUT
V_OH High-level output voltage
I_OH = 100 µA
V_OL Low-level output voltage
I_OL = 100 µA
DIGITAL OUTPUTS – LVDS INTERFACE (OUT1P/M TO OUT8P/M, ADCLKP/M, LCLKP/M)
AVDD – 0.05
V
0.05
V
V_ODH High-level output differential voltage
V_ODL Low-level output differential voltage
V_OCM Output common-mode voltage
With external 100-Ω termination
With external 100-Ω termination
275
–465
1000
370 465 mV
–370 –275 mV
1200 1400 mV
(1) CS, SDATA, SCLK have internal 300-kΩ pulldown resistor.
7.9 Timing Requirements⁽¹⁾
Typical values are at 25°C, AVDD = 3.3 V, LVDD = 1.8 V, sampling frequency = 100 MSPS, sine wave input clock = 1.5 Vpp
clock amplitude, C_LOAD = 5 pF⁽²⁾, R_LOAD = 100 Ω⁽³⁾, unless otherwise noted. MIN and MAX values are across the full
temperature range, T_MIN = –40°C to T_MAX = 85°C, AVDD = 3.3 V, LVDD = 1.7 V to 1.9 V
MIN TYP MAX UNIT
t_j
Aperture jitter
t_A
Aperture delay
Time delay between rising edge of input clock and the actual
sampling instant
220
fs rms
3
ns
Wake-up time
Time to valid data after coming out of STANDBY mode
Time to valid data after coming out of global power down
10
μs
60
ADC latency
2 WIRE, 8× SERIALIZATION ⁽⁴⁾
Latency of ADC alone, excludes the delay from input clock to
output clock (t_PDI), Figure 3
16
Clock
cycles
t_su
Data setup time
Data valid (5) to zero-crossing of LCLKP
0.23
ns
t_h
Data hold time
Zero-crossing of LCLKP to data becoming invalid⁽⁵⁾
0.31
ns
t_PDI
Clock propagation
delay
Input clock rising edge crossover to output frame clock ADCLKP
rising edge crossover, t_PDI = (t_s/4) + t_delay
6.8 8.8 10.8 ns
Variation of t_PDI
Between two devices at same temperature and LVDD supply
±0.6
ns
LVDS bit clock duty
cycle
Duty cycle of differential clock, (LCLKP-LCLKM)
50%
t_RISE
t_FALL
Data rise time,
Data fall time
Rise time measured from –100 mV to 100 mV,
Fall time measured from 100 mV to –100 mV
10 MSPS ≤ Sampling frequency ≤ 100 MSPS
0.17
ns
t_CLKRISE
t_CLKFALL
Output clock rise time,
Output clock fall time
Rise time measured from –100 mV to 100 mV
Fall time measured from 100 mV to –100 mV
10 MSPS ≤ Sampling frequency ≤ 100 MSPS
0.2
ns
(1) Timing parameters are ensured by design and characterization and not tested in production.
(2) C_LOAD is the effective external single-ended load capacitance between each output pin and ground.
(3) R_LOAD is the differential load resistance between the LVDS output pair.
(4) Measurements are done with a transmission line of 100-Ω characteristic impedance between the device and the load. Setup and hold
time specifications take into account the effect of jitter on the output data and clock.
(5) Data valid refers to logic HIGH of 100 mV and logic LOW of –100 mV.
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