ADS5263_15 Datasheet, PDF (1/84 Pages) Texas Instruments – Quad Channel 16-Bit, 100-MSPS High-SNR ADC

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ADS5263
SLAS760D – MAY 2011 – REVISED NOVEMBER 2015
ADS5263 Quad Channel 16-Bit, 100-MSPS High-SNR ADC
1 Features
•1 Maximum Sample Rate: 100 MSPS
• Programmable Device Resolution
– Quad-Channel, 16-Bit, High-SNR Mode
– Quad-Channel, 14-Bit, Low-Power Mode
• 16-Bit High-SNR Mode
– 1.4 W Total Power at 100 MSPS
– 355 mW / Channel
– 4 Vpp Full-scale Input
– 85-dBFS SNR at f_in = 3 MHz, 100 MSPS
• 14-Bit Low-Power Mode
– 785 mW Total Power at 100 MSPS
– 195 mW/Channel
– 2-Vpp Full-Scale Input
– 74-dBFS SNR at f_in = 10 MHz
– Integrated Clamp (for interfacing to CCD
sensors)
• Low-Frequency Noise Suppression
• Digital Processing Block
– Programmable FIR Decimation Filters
– Programmable Digital Gain: 0 dB to 12 dB
– 2- or 4-Channel Averaging
• Programmable Mapping Between ADC Input
Channels and LVDS Output Pins—Eases Board
Design
• Variety of Test Patterns to Verify Data Capture by
FPGA/Receiver
• Serialized LVDS Outputs
• Internal and External References
• 3.3-V Analog Supply
• 1.8-V Digital Supply
• Recovers From 6-dB Overload Within 1 Clock
Cycle
• Package:
– 9-mm × 9-mm 64-Pin QFN
– Non-Magnetic Package Option for MRI
Systems
• CMOS Technology
2 Applications
• Medical Imaging – MRI
• Spectroscopy
• CCD Imaging
3 Description
Using CMOS process technology and innovative
circuit techniques, the ADS5263 is designed to
operate at low power and give very high SNR
performance with a 4-Vpp full-scale input. Using a
low-noise 16-bit front-end stage followed by a 14-bit
ADC, the device gives 85-dBFS SNR up to 10 MHz
and better than 80-dBFS SNR up to 30 MHz.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
ADS5263
VQFN (64)
9.00 mm × 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
ADS5263 Block Diagram
IN1B_P
IN1A_P
IN1A_M
IN1B_M
ADS5263
16-Bit
FE
16-Bit ADC
14-Bit
ADC
DIGITAL
SERIALIZER
SERIALIZER
IN4B_P
IN4A_P
IN4A_M
IN4B_M
CLKP
CLKM
16-Bit
FE
14-Bit
ADC
DIGITAL
SERIALIZER
SERIALIZER
ADC Clocking
Sync Signal
CLOCK
BUFFER
CLOCKGEN
BIT CLOCK 8X
FRAME CLOCK 1X
REFERENCE
ADC CONTROL
SERIAL
INTERFACE
OUT1P
OUT1M
OUT2P
OUT2M
OUT7P
OUT7M
OUT8P
OUT8M
LCLKP
LCLKM
ADCLKP
ADCLKM
SDOUT
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.