TMS470R1A288PGEA Datasheet, PDF (10/62 Pages) Texas Instruments – 16/32-Bit RISC Flash Microcontroller

TMS470R1A288
16/32-Bit RISC Flash Microcontroller
SPNS106B – SEPTEMBER 2005 – REVISED AUGUST 2006
www.ti.com
Table 2. Terminal Functions
TERMINAL
NAME
PZ
HET[0]
51
HET[1]
50
HET[2]
49
HET[3]
46
HET[4]
45
HET[5]
44
HET[6]
6
HET[7]
7
HET[8]
8
HET[18]
9
HET[20]
12
HET[22]
13
CAN1SRX
58
CAN1STX
59
CAN2SRX
37
CAN2STX
38
C2SILPN
14
C2SIRX
15
C2SITX
16
GIOA[0]/INT[0]
99
GIOA[1]/INT[1]/ECLK 96
GIOA[2]/INT[2]
95
GIOA[3]/INT[3]
94
GIOA[4]/INT[4]
89
GIOA[5]/INT[5]
67
GIOA[6]/INT[6]
55
GIOA[7]/INT[7]
56
GIOB[0]/DMAREQ[0] 30
GIOC[0]/EBOE
-
GIOC[1]/EBWR[0]
-
GIOC[2]/EBWR[1]
-
GIOC[3]/EBCS[5]
-
GIOC[4]/EBCS[6]
-
PGE
73
72
71
66
65
63
9
11
12
15
18
19
83
84
54
55
21
22
24
141
136
134
133
127
98
78
79
43
135
128
126
120
119
INPUT
VOLTAGE ^{(1) (2)}
OUTPUT
CURRENT ⁽³⁾
INTERNAL
PULLUP/
PULLDOWN
HIGH-END TIMER (HET)
DESCRIPTION
3.3-V
2 mA -z
Timer input capture or output compare. The
HET[8:0,18,20,22] applicable pins can be
programmed as general-purpose input/output
(GIO) pins. All are high-resolution pins.
The high-resolution (HR) SHARE feature allows
even HR pins to share the next higher odd HR
pin structures. This HR sharing is independent of
whether or not the odd pin is available
externally. If an odd pin is available externally
and shared, then the odd pin can only be used
as a general-purpose I/O. For more information
on HR SHARE, see the TMS470R1x High-End
Timer (HET) Reference Guide (literature number
SPNU199).
STANDARD CAN CONTROLLER (SCC)
5 V tolerant
4 mA
SCC1 receive pin or GIO pin
3.3-V
2 mA -z
SCC1 transmit pin or GIO pin
5 V tolerant
4 mA
SCC2 receive pin or GIO pin
3.3-V
2 mA -z
SCC 2 transmit pin or GIO pin
CLASS II SERIAL INTERFACE (C2SIB)
3.3-V
2 mA -z
C2SIb module loopback enable pin or GIO pin
5 V tolerant
4 mA
C2SIb module receive data input pin or GIO pin
3.3-V
2 mA -z
C2SIb module transmit data output pin or GIO
pin
GENERAL-PURPOSE I/O (GIO)
5 V tolerant
4 mA
General-purpose input/output pins.
GIOA[7:0]/INT[7:0] are interrupt-capable pins.
GIOA[1]/INT[1]/ECLK pin is multiplexed with the
external clock-out function of the external clock
prescale (ECP) module.
3.3-V
2 mA -z
IPD (20 µA)
GIOB[0], GIOC[4:0], GIOD[5:0], GIOE[7:0:],
GIOF[7:0], GIOG[7:0], and GIOH[5:0] are
multiplexed with the expansion bus module.
See Table 7.
(1) PWR = power, GND = ground, REF = reference voltage, NC = no connect
(2) All I/O pins, except RST , are configured as inputs while PORRST is low and immediately after PORRST goes high.
(3) IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST
state.)
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