BQ28Z560-R1_14 Datasheet, PDF (10/61 Pages) Texas Instruments – Single Cell Li-Ion Battery Gas Gauge

bq28z560-R1
Not Recommended For New Designs
SLUSBD3 – APRIL 2013
www.ti.com
I²C SERIAL COMMUNICATION TIMING CHARACTERISTICS
T_A = –40 to +85ºC, V_BAT = 2.7 V to 5.5 V; Typical values stated, where T_A = 25ºC and V_BAT = 3.6 V (unless otherwise noted).
Capacitance on serial interface pins SCL and SDA are 10 pF unless otherwise specified ⁽¹⁾.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t_r
t_f
t_w(H)
t_w(L)
t_su(STA)
t_d(STA)
t_su(DAT)
t_h(DAT)
t_su(STOP)
t_(BUF)
SCL/SDA rise time
SCL/SDA fall time
SCL pulse width (high)
SCL pulse width (low)
Setup for repeated start
Start to first falling edge of SCL
Data setup time
Data hold time
Setup time for stop
Bus free time between stop and
start
300
ns
300
ns
600
ns
1.3
μs
600
ns
600
ns
1
μs
0
ns
600
ns
1.3
μs
f_(SCL)
Clock frequency
100
kHz
(1) Parameters specified by worst-case test program execution in FAST mode.
t_{su (STA)}
t_w(H)
t_w(L)
t_f
tr
t_(BUF)
SCL
SDA
t_{d (STA)}
REPEATED
START
t_r
t_h(DAT) t_su (DAT)
t_f
Figure 5. I²C Serial Communication Timing
t_su(STOP)
STOP
START
I²C BUS COMMUNICATION
The 2-wire communication bus supports a slave-only device in a single- or multi-slave configuration with a single-
or multi-master configuration. The device can be part of a shared bus by the unique setting of the 7-bit slave
address. The 2-wire communication is bi-directional, consisting of a serial data line (SDA) and serial clock line
(SCL). In RECEIVE mode, the SDA terminal operates as an input; whereas, when the device is returning data to
the master, the SDA operates as an open drain output with an external resistive pull-up. The master device
controls the initiation of the transaction on the bus line.
Data Transfer: Each data bit is transferred during an SCL clock cycle (transition from low-to-high and then high-
to-low). The data signal on the SDA (logic level) must be stable during the high period of the SCL clock pulse. A
change in the SDA logic when SCL is high is interpreted as a START or STOP control signal. If a transfer is
interrupted by a STOP condition, the partial byte transmission shall not be latched. Only the prior messages
transmitted and acknowledged are latched.
Data Format: The data is an 8-bit format with the most significant bit (MSB) first, and the least significant bit
(LSB) followed by an Acknowledge bit. If the slave cannot receive or transmit any byte of data until it services a
priority interrupt, it can pull the SCL line low to force the master device into wait state. The slave, once ready to
resume data transfer, can release the SCL line (get out of wait state).
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