SN74BCT979 Datasheet, PDF (1/10 Pages) Texas Instruments – 9-BIT REGISTERED BTL TRANSCEIVER WITH PARITY GENERATOR/CHECKER

• BiCMOS Design Significantly Reduces I_CCZ
• ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
• Support IEEE BTL Standard 1194.1-1991
• Open-Collector B Port Drives Load
Impedances as Low as 10 Ω
• BTL Logic Level 1-V Bus Swing Reduces
Power Consumption
• Latchable Transceiver With Output Sink
of 24 mA at the A Bus and 100 mA at the
B Bus
• Option to Generate and Check Parity or
Feed-Through Data/Parity in Directions
A to B or B to A
• Independent Latch Enables for A-to-B
and B-to-A Directions
• Select Pin for ODD/EVEN Parity
• ERRA and ERRB Output Pins for Parity
Checking
• Ability to Simultaneously Generate and
Check Parity
• Packaged in 300-mil Plastic Shrink
Small-Outline (DL) Package
SN74BCT979
9ĆBIT REGISTERED BTL TRANSCEIVER
WITH PARITY GENERATOR/CHECKER
SCBS115A − OCTOBER 1990 − REVISED NOVEMBER 1993
DL PACKAGE
(TOP VIEW)
V_CC 1
AI1 2
AO1 3
AI2 4
AO2 5
GND 6
AI3 7
AO3 8
AI4 9
AO4 10
AI5 11
GND 12
AO5 13
AI6 14
AO6 15
AI7 16
AO7 17
GND 18
AI8 19
AO8 20
APARI 21
APARO 22
V_CC 23
LEBA 24
48 OEBA
47 LEAB
46 B1
45 GND
44 GND
43 B2
42 ERRA
41 B3
40 GND
39 GND
38 B4
37 ODD/EVEN
36 B5
35 SEL
34 B6
33 GND
32 GND
31 B7
30 ERRB
29 B8
28 GND
27 GND
26 BPAR
25 OEAB
description
The SN74BCT979 is a 9-bit to 9-bit parity transceiver with transparent latches. The device can operate as a
feed-through transceiver, or it can generate/check parity from the 8-bit data bus in either direction. It has a
guaranteed current-sinking capability of 24 mA at the A bus and 100 mA at the open-collector B bus.
The SN74BCT979 features independent latch-enable (LEAB, LEBA) inputs for the A-to-B direction and the
B-to-A direction, an ODD/EVEN input to select odd or even parity, and separate error-signal (ERRA, ERRB)
outputs for checking parity.
When communication between buses occurs, parity is generated and passed on to either bus as APARO or
BPAR. Error detection of the parity generated from AI1−AI8 and B1−B8 can be checked by ERRA and ERRB,
providing LEAB and LEBA are high and the mode select (SEL) is low. If SEL is high, the communication between
buses is in a feed-through mode where parity is still generated and checked as ERRA and ERRB.
The SN74BCT979 features open-collector driver outputs (B port) with a series Schottky diode to reduce
capacitive loading to the bus. By using a 2-V pullup on the bus, the output signal swing will be approximately
1 V, which reduces the power necessary to drive the bus load capacitance. The driver outputs are capable of
driving an equivalent dc load of as low as 10 Ω.
The transceiver has a precision threshold set by an internal bandgap reference to give accurate input thresholds
over V_CC and temperature variations.
This transceiver is compatible with backplane transceiver logic (BTL) technology at significantly reduced power
dissipation per channel.
The SN74BCT979 is characterized for operation from 0°C to 70°C.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  1993, Texas Instruments Incorporated
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