TMS320C6711B Datasheet, PDF (96/132 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSORS

TMS320C6711, TMS320C6711B, TMS320C6711C
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSORS
SPRS088O − FEBRUARY 1999 − REVISED NOVEMBER 2005
RESET TIMING [C6711/11B] (CONTINUED)
CLKOUT1
CLKOUT2
RESET
1
14
15
2
3
ECLKIN†
4
5
EMIF Z Group‡
6
7
EMIF High Group‡
8
9
EMIF Low Group‡
10
11
High Group‡
12
13
Z Group‡
HD[8, 4:3]§
† _{ECLKIN should be provided during reset in order to drive EMIF signals to the correct reset values. ECLKOUT continues to clock as long as}
ECLKIN is provided.
‡ _{EMIF Z group consists of:}
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE
EMIF high group consists of: HOLDA
EMIF low group consists of: BUSREQ
High group consists of:
HRDY and HINT
Z group consists of:
HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, FSR1, TOUT0, and TOUT1.
§ _{HD[8, 4:3] are the endianness and boot configuration pins during device reset.}
Figure 42. Reset Timing [C6711/11B]
96
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443