TMS320C6711B Datasheet, PDF (95/132 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSORS

TMS320C6711, TMS320C6711B, TMS320C6711C
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSORS
SPRS088O − FEBRUARY 1999 − REVISED NOVEMBER 2005
RESET TIMING [C6711/11B]
timing requirements for reset^† (see Figure 42)
–100
NO.
–150
UNIT
MIN MAX
1 tw(RST)
Width of the RESET pulse (PLL stable)‡
Width of the RESET pulse (PLL needs to sync up)§
10P
ns
250
µs
14 tsu(HD)
Setup time, HD boot configuration bits valid before RESET high¶
2P
ns
15 th(HD)
Hold time, HD boot configuration bits valid after RESET high¶
2P
ns
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.}
‡ _{This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x4 when CLKIN and PLL are stable.}
§ _{This parameter applies to CLKMODE x4 only (it does not apply to CLKMODE x1). The RESET signal is not connected internally to the clock PLL}
circuit. The PLL, however, may need up to 250 µs to stabilize following device power up or after PLL configuration has been changed. During
that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times.
¶ _{HD[4:3] are the boot configuration pins during device reset.}
switching characteristics over recommended operating conditions during reset^†#|| (see Figure 42)
NO.
PARAMETER
–100
–150
MIN
UNIT
MAX
2 td(RSTL-ECKI) Delay time, RESET low to ECLKIN synchronized internally
2P + 3E 3P + 4E ns
3 td(RSTH-ECKI) Delay time, RESET high to ECLKIN synchronized internally
2P + 3E 3P + 4E ns
4 td(RSTL-EMIFZHZ) Delay time, RESET low to EMIF Z group high impedance
2P + 3E
ns
5 td(RSTH-EMIFZV) Delay time, RESET high to EMIF Z group valid
3P + 4E ns
6 td(RSTL-EMIFHIV) Delay time, RESET low to EMIF high group invalid
2P + 3E
ns
7 td(RSTH-EMIFHV) Delay time, RESET high to EMIF high group valid
3P + 4E ns
8 td(RSTL-EMIFLIV) Delay time, RESET low to EMIF low group invalid
2P + 3E
ns
9 td(RSTH-EMIFLV) Delay time, RESET high to EMIF low group valid
3P + 4E ns
10 td(RSTL-HIGHIV) Delay time, RESET low to high group invalid
2P
ns
11 td(RSTH-HIGHV) Delay time, RESET high to high group valid
4P ns
12 td(RSTL-ZHZ) Delay time, RESET low to Z group high impedance
2P
ns
13 td(RSTH-ZV) Delay time, RESET high to Z group valid
2P
ns
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.}
# _{E = ECLKIN period in ns}
|| _{EMIF Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE}
EMIF high group consists of: HOLDA
EMIF low group consists of: BUSREQ
High group consists of:
HRDY and HINT
Z group consists of:
HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, FSR1, TOUT0, and TOUT1.
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