TMS320C6711B Datasheet, PDF (52/132 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSORS

TMS320C6711, TMS320C6711B, TMS320C6711C
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSORS
SPRS088O − FEBRUARY 1999 − REVISED NOVEMBER 2005
PLL and PLL controller [C6711C only] (continued)
PLLCSR Register (0x01B7 C100)
31
28 27
24 23
20 19
Reserved
R−0
15
12 11
87
6
5
4
3
Reserved
STABLE
Reserved
PLLRST
R−0
R−x
R−0
RW−1
Legend: R = Read only, R/W = Read/Write; -n = value after reset
2
Reserved
R/W−0
1
PLLPWRDN
R/W−0b
16
0
PLLEN
RW−0
BIT #
31:7
6
5:4
3
2
1
0
NAME
Reserved
STABLE
Reserved
PLLRST
Reserved
PLLPWRDN
PLLEN
Table 32. PLL Control/Status Register (PLLCSR)
DESCRIPTION
Reserved. Read-only, writes have no effect.
Oscillator Input Stable. This bit indicates if the OSCIN/CLKIN input has stabilized.
0 – OSCIN/CLKIN input not yet stable. Oscillator counter is not finished counting (default).
1 – OSCIN/CLKIN input stable.
Reserved. Read-only, writes have no effect.
Asserts RESET to PLL
0 – PLL Reset Released.
1 – PLL Reset Asserted (default).
Reserved. The user must write a “0” to this bit.
Select PLL Power Down
0 – PLL Operational (default).
1 – PLL Placed in Power-Down State.
PLL Mode Enable
0 – Bypass Mode (default). PLL disabled.
Divider D0 and PLL are bypassed. SYSCLK1/SYSCLK2/SYSCLK3 are divided down
directly from input reference clock.
1 – PLL Enabled.
Divider D0 and PLL are not bypassed. SYSCLK1/SYSCLK2/SYSCLK3 are divided down
from PLL output.
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