OMAPL138B-EP_15 Datasheet, PDF (94/284 Pages) Texas Instruments – OMAPL138B C6-Integra DSP+ARM Processor

OMAPL138B-EP
SPRS815C – DECEMBER 2011 – REVISED APRIL 2013
www.ti.com
5.7 Interrupts
The device has a large number of interrupts to service the needs of its many peripherals and subsystems.
Both the ARM and C674x CPUs are capable of servicing these interrupts equally. The interrupts can be
selectively enabled or disabled in either of the controllers. Also, the ARM and DSP can communicate with
each other through interrupts controlled by registers in the SYSCFG module.
5.7.1 ARM CPU Interrupts
The ARM9 CPU core supports two direct interrupts: FIQ and IRQ. The ARM Interrupt Controller (AINTC)
extends the number of interrupts to 100, and provides features like programmable masking, priority,
hardware nesting support, and interrupt vector generation.
5.7.1.1 ARM Interrupt Controller (AINTC) Interrupt Signal Hierarchy
The ARM Interrupt controller organizes interrupts into the following hierarchy:
• Peripheral Interrupt Requests
– Individual Interrupt Sources from Peripherals
• 101 System Interrupts
– One or more Peripheral Interrupt Requests are combined (fixed configuration) to generate a
System Interrupt.
– After prioritization, the AINTC will provide an interrupt vector based unique to each System Interrupt
• 32 Interrupt Channels
– Each System Interrupt is mapped to one of the 32 Interrupt Channels
– Channel Number determines the first level of prioritization, Channel 0 is highest priority and 31
lowest.
– If more than one system interrupt is mapped to a channel, priority within the channel is determined
by system interrupt number (0 highest priority)
• Host Interrupts (FIQ and IRQ)
– Interrupt Channels 0 and 1 generate the ARM FIQ interrupt
– Interrupt Channels 2 through 31 Generate the ARM IRQ interrupt
• Debug Interrupts
– Two Debug Interrupts are supported and can be used to trigger events in the debug subsystem
– Sources can be selected from any of the System Interrupts or Host Interrupts
5.7.1.2 AINTC Hardware Vector Generation
The AINTC also generates an interrupt vector in hardware for both IRQ and FIQ host interrupts. This may
be used to accelerate interrupt dispatch. A unique vector is generated for each of the 100 system
interrupts. The vector is computed in hardware as:
VECTOR = BASE + (SYSTEM INTERRUPT NUMBER × SIZE)
Where BASE and SIZE are programmable. The computed vector is a 32-bit address which may
dispatched to using a single instruction of type LDR PC, [PC, #-<offset_12>] at the FIQ and IRQ vector
locations (0xFFFF0018 and 0xFFFF001C respectively).
94
Peripheral Information and Electrical Specifications
Copyright © 2011–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: OMAPL138B-EP