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OMAPL138B-EP_15 Datasheet, PDF (2/284 Pages) Texas Instruments – OMAPL138B C6-Integra DSP+ARM Processor | |||
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OMAPL138B-EP
SPRS815C â DECEMBER 2011 â REVISED APRIL 2013
www.ti.com
Program Redirection
⢠Software Support
â TI DSP/BIOSâ¢
â Chip Support Library and DSP Library
⢠128K-Byte RAM Shared Memory
⢠1.8V or 3.3V LVCMOS IOs (except for USB and
DDR2 interfaces)
⢠Two External Memory Interfaces:
â EMIFA
⢠NOR (8-/16-Bit-Wide Data)
⢠NAND (8-/16-Bit-Wide Data)
⢠16-Bit SDRAM With 128 MB Address
Space
â DDR2/Mobile DDR Memory Controller
⢠16-Bit DDR2 SDRAM With 512 MB
Address Space or
⢠16-Bit mDDR SDRAM With 256 MB
Address Space
⢠Three Configurable 16550 type UART Modules:
â With Modem Control Signals
â 16-byte FIFO
â 16x or 13x Oversampling Option
⢠LCD Controller
⢠Two Serial Peripheral Interfaces (SPI) Each
With Multiple Chip-Selects
⢠Two Multimedia Card (MMC)/Secure Digital (SD)
Card Interface with Secure Data I/O (SDIO)
Interfaces
⢠Two Master/Slave Inter-Integrated Circuit (I2C
Busâ¢)
⢠One Host-Port Interface (HPI) With 16-Bit-Wide
Muxed Address/Data Bus For High Bandwidth
⢠Programmable Real-Time Unit Subsystem
(PRUSS)
â Two Independent Programmable Realtime
Unit (PRU) Cores
⢠32-Bit Load/Store RISC architecture
⢠4K Byte instruction RAM per core
⢠512 Bytes data RAM per core
⢠PRU Subsystem (PRUSS) can be disabled
via software to save power
⢠Register 30 of each PRU is exported from
the subsystem in addition to the normal
R31 output of the PRU cores.
â Standard power management mechanism
⢠Clock gating
⢠Entire subsystem under a single PSC
clock gating domain
â Dedicated interrupt controller
â Dedicated switched central resource
⢠USB 1.1 OHCI (Host) With Integrated PHY
(USB1)
⢠USB 2.0 OTG Port With Integrated PHY (USB0)
â USB 2.0 High-/Full-Speed Client
â USB 2.0 High-/Full-/Low-Speed Host
â End Point 0 (Control)
â End Points 1,2,3,4 (Control, Bulk, Interrupt or
ISOC) Rx and Tx
⢠One Multichannel Audio Serial Port:
â Two Clock Zones and 16 Serial Data Pins
â Supports TDM, I2S, and Similar Formats
â DIT-Capable
â FIFO buffers for Transmit and Receive
⢠Two Multichannel Buffered Serial Ports:
â Supports TDM, I2S, and Similar Formats
â AC97 Audio Codec Interface
â Telecom Interfaces (ST-Bus, H100)
â 128-channel TDM
â FIFO buffers for Transmit and Receive
⢠10/100 Mb/s Ethernet MAC (EMAC):
â IEEE 802.3 Compliant
â MII Media Independent Interface
â RMII Reduced Media Independent Interface
â Management Data I/O (MDIO) Module
⢠Video Port Interface (VPIF):
â Two 8-bit SD (BT.656), Single 16-bit or Single
Raw (8-/10-/12-bit) Video Capture Channels
â Two 8-bit SD (BT.656), Single 16-bit Video
Display Channels
⢠Universal Parallel Port (uPP):
â High-Speed Parallel Interface to FPGAs and
Data Converters
â Data Width on Each of Two Channels is 8- to
16-bit Inclusive
â Single Data Rate or Dual Data Rate Transfers
â Supports Multiple Interfaces with START,
ENABLE and WAIT Controls
⢠Serial ATA (SATA) Controller:
â Supports SATA I (1.5 Gbps) and SATA II (3.0
Gbps)
â Supports all SATA Power Management
Features
â Hardware-Assisted Native Command
Queueing (NCQ) for up to 32 Entries
â Supports Port Multiplier and Command-
Based Switching
⢠Real-Time Clock With 32 KHz Oscillator (1) and
Separate Power Rail
⢠Three 64-Bit General-Purpose Timers (Each
Configurable as Two 32-Bit Timers)
⢠One 64-bit General-Purpose/Watchdog Timer
(Configurable as Two 32-bit General-Purpose
Timers)
⢠Two Enhanced Pulse Width Modulators
(eHRPWM):
(1) Crystal oscillator cannot be operated beyond 105°C.
2
OMAPL138B C6-Integra⢠DSP+ARM® Processor
Copyright © 2011â2013, Texas Instruments Incorporated
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