TMS320VC5509_08 Datasheet, PDF (93/124 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
5.8.3 Warm Reset
Table 5−16 and Table 5−17 assume testing over recommended operating conditions (see Figure 5−16).
Table 5−16. Reset Timing Requirements
NO.
R4 tw(RSL)
Pulse width, reset low
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 144 MHz, use P = 6.94 ns.}
MIN MAX UNIT
3P†
ns
Table 5−17. Reset Switching Characteristics^†
NO.
PARAMETER
MIN
MAX UNIT
R5 td(RSTH-BKV)
R6 td(RSTH-HIGHV)
R7 td(RSTL-ZIV)
R8 td(RSTH-ZV)
Delay time, reset high to BK group valid‡
Delay time, reset high to High group valid§
Delay time, reset low to Z group invalid¶
Delay time, reset high to Z group valid¶
38P + 6 ns
38P + 6 ns
20 ns
38P + 6 ns
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 144 MHz, use P = 6.94 ns.}
‡ _{BK group: Pins with bus keepers, holds previous state during reset. Following low-to-high transition of RESET, these pins go to their post-reset}
logic state.
BK group pins: A’[0], A[15:0], D[15:0], C[14:2], C0, GPIO5, S13, and S23
§ _{High group: Following low-to-high transition of RESET, these pins go to logic-high state.}
High group pins: C1[HPI.HINT], XF
¶ _{Z group: Bidirectional pins which become input or output pins. Following low-to-high transition of RESET, these pins go to high-impedance state.}
Z group pins: C1[EMIF.AOE], GPIO[7:6, 4:0], TIN/TOUT0, SDA, SCL, CLKR0, FSRX0, CLKX0, DX0, FSX0, S[25:24, 22:20, 15:14, 12:10],
A[20:16]
RESET
R5
BK Group†
High Group‡
R7
Z Group§
R6
R8
† _{BK group pins: A’[0], A[15:0], D[15:0], C[14:2], C0, GPIO5, S13, and S23}
‡ _{High group pins: C1[HPI.HINT], XF}
§ _{Z group pins: C1[EMIF.AOE], GPIO[7:6, 4:0], TIN/TOUT0, SDA, SCL, CLKR0, FSRX0, CLKX0, DX0, FSX0, S[25:24, 22:20, 15:14, 12:10],}
A[20:16]
Figure 5−16. Reset Timings
April 2001 − Revised January 2008
SPRS163H
93