TMS320VC5509_08 Datasheet, PDF (111/124 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

HCS
H1
H2
HAS
H5
H6
HDS
H9
H10
H3
H4
HR/W
Electrical Specifications
HBE[1:0]
HCNTL[1:0]
HPI.HD[15:0]
(Write)
HRDY
HPIA
Contents
HPID
Contents
Valid (01)
Valid (01)
H7
H8
Write Data
H20
H19
Write Data
H20
H19
n
d(n)
n+1
d(n+1)
n+2
d(n+2)
NOTES: A. During autoincrement mode, although the EHPI internally increments the memory address, reads of the HPIA register by the
host will always indicate the base address.
B. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur
concurrent with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied permanently active and HCS is used as a strobe,
the timing requirements shown for HDS apply to HCS. Operation with HCS as a strobe is not recommended.
Figure 5−33. EHPI Multiplexed Memory (HPID) Access Write Timings With Autoincrement
April 2001 − Revised January 2008
SPRS163H 111