TMS320VC5509_08 Datasheet, PDF (43/124 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Functional Overview
3.5.3 Parallel Port Signal Routing
The 5509 allows access to 16-bit-wide (read and write) asynchronous memory and 16-bit-wide SDRAM. For
16-bit-wide memories, EMIF.A[0] is kept low and is not used. To provide as many address pins as possible,
the 5509 routes the parallel port signals as shown in Figure 3−7.
Figure 3−7 shows the addition of the A′[0] signal in the BGA package. This pin is used for asynchronous
memory interface only, while the A[0] pin is used with HPI or GPIO. Figure 3−8 summarizes the use of the
parallel port signals for memory interfacing.
EMIF.A[0]
A’[0] (BGA only)
GPIO.A[0]
HPI.HA[0]
EMIF.A[13:1]
HPI.HA[13:1]
GPIO.A[13:1]
A[0]
A[13:1]
EMIF.A[14]
GPIO.A[14]
A[14] (BGA only)
EMIF.A[15]
GPIO.A[15]
A[15] (BGA only)
EMIF.A[20:16]
A[20:16] (BGA only)
Figure 3−7. Parallel Port Signal Routing
April 2001 − Revised January 2008
SPRS163H
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