TMS320VC5509_08 Datasheet, PDF (113/124 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
5.16 I²C Timings
Table 5−39 and Table 5−40 assume testing over recommended operating conditions (see Figure 5−35 and
Figure 5−36).
Table 5−39. I²C Signals (SDA and SCL) Timing Requirements
STANDARD
FAST
NO.
MODE
MODE
UNIT
MIN MAX
MIN
MAX
IC1 tc(SCL)
Cycle time, SCL
10
IC2
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low for a repeated START
condition
4.7
2.5
µs
0.6
µs
IC3 th(SCLL-SDAL)
Hold time, SCL low after SDA low for a START and a repeated
START condition
4
0.6
µs
IC4 tw(SCLL)
Pulse duration, SCL low
4.7
1.3
µs
IC5 tw(SCLH)
IC6 tsu(SDA-SCLH)
IC7 th(SDA-SCLL)
Pulse duration, SCL high
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low
4
0.6
µs
250
100†
ns
0‡
0‡
0.9§ µs
IC8
IC9
IC10
IC11
IC12
tw(SDAH)
tr(SDA)
tr(SCL)
tf(SDA)
tf(SCL)
Pulse duration, SDA high between STOP and START conditions
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
4.7
1.3
1000
1000
300
300
20 + 0.1Cb¶
20 + 0.1Cb¶
20 + 0.1Cb¶
20 + 0.1Cb¶
µs
300 ns
300 ns
300 ns
300 ns
IC13 tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition)
4.0
0.6
µs
IC14 tw(SP)
Pulse duration, spike (must be suppressed)
0
50 ns
IC15 Cb¶
Capacitive load for each bus line
400
400 pF
† _{A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be met.}
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period
of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 = 1250 ns (according to the Standard-mode
I2C-Bus Specification) before the SCL line is released.
‡ _{A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined}
region of the falling edge of SCL.
§ _{The maximum th(SDA-SCLL) has only to be met if the device does not stretch the LOW period [tw(SCLL)] of the SCL signal.}
¶ _{Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.}
SDA
SCL
IC11
IC8
IC4
IC10
IC6
IC5
IC1
IC12
IC3
IC7
IC2
IC3
Stop Start
Repeated
Start
Figure 5−35. I²C Receive Timings
I2C Bus is a trademark of Koninklijke Philips Electronics N.V.
April 2001 − Revised January 2008
IC9
IC14
IC13
Stop
SPRS163H 113