TLC2543CDWR Datasheet, PDF (9/34 Pages) Texas Instruments – 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS

TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001
PARAMETER MEASUREMENT INFORMATION
CS
(see Note A)
I/O
CLOCK
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 1
2
3
4
5
6
7
8
11
12
1
Access Cycle B
Sample Cycle B
DATA
A11
A10 A9
A8
A7
A6
A5
A4
A1
A0
Hi-Z State
B11
OUT
Previous Conversion Data
DATA
INPUT
ÎÎÎÎ^MÎÎ^SBÎÎÎÎÎÎÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
LSB
B7
B6
B5
B4
B3
B2
B1
B0
MSB
LSB
ÎÎÎÎ_C7ÎÎÎÎ
EOC
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
t(conv)
Conversion Value
A/D Conversion
Initialize
Interval
Initialize
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input signals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 9. Timing for 12-Clock Transfer Using CS With MSB First
CS
(see Note A)
I/O
CLOCK
1
2
3
4
Access Cycle B
5
6
7
8
11
12
Sample Cycle B
DATA
OUT
A11
A10 A9
A8
A7
A6
A5
A4
A1
A0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _DATA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ INPUT
MSB
Previous Conversion Data
B7
B6
B5
B4
B3
B2
B1
B0
LSB
MSB
LSB
1
Low Level
B11
ÎÎÎÎÎÎÎÎÎ_C7ÎÎÎÎÎÎ
EOC
Initialize
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
t(conv)
A/D Conversion
Interval _Initialize
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input signals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 10. Timing for 12-Clock Transfer Not Using CS With MSB First
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
9