TLC2543CDWR Datasheet, PDF (11/34 Pages) Texas Instruments – 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS

TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001
PARAMETER MEASUREMENT INFORMATION
CS
(see Note A)
I/O
CLOCK
1
2
3
4
Access Cycle B
5
6
7
8
15
16
1
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Sample Cycle B}
DATA
OUT
A15
A14 A13
A12 A11
A10 A9
A8
A1
A0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _DATA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^INPUT
MSB
Previous Conversion Data
LSB
B7
B6
B5
B4
B3
B2
B1
B0
MSB
LSB
Hi-Z State
B15
ÎÎÎÎÎ
C7
EOC
Initialize
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
t(conv)
A/D Conversion
Interval
Initialize
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input signals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 13. Timing for 16-Clock Transfer Using CS With MSB First
CS
(see Note A)
I/O
CLOCK
1
2
3
4
Access Cycle B
5
6
7
8
15
16
Sample Cycle B
DATA
OUT
A15
A14 A13 A12 A11 A10 A9
A8
A1
A0
ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _DATA
ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^INPUT
MSB
Previous Conversion Data
LSB
B7
B6
B5
B4
B3
B2
B1
B0
MSB
LSB
1
Low Level
B15
ÎÎÎÎÎÎÎÎÎÎ
C7
EOC
Initialize
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
t(conv)
A/D Conversion
Interval
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input signals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 14. Timing for 16-Clock Transfer Not Using CS With MSB First
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