TLC2543CDWR Datasheet, PDF (10/34 Pages) Texas Instruments – 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS

TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001
PARAMETER MEASUREMENT INFORMATION
CS
(see Note A)
I/O CLOCK
1
2
3
4
Access Cycle B
5
6
7
Sample Cycle B
8 _{ÎÎÎÎÎÎÎÎÎÎÎÎ} 1
DATA OUT
A7
A6
A5
A4
A3
A2
A1
A0
Hi-Z
B7
Previous Conversion Data
MSB
LSB
DATAINPUT _{ÎÎÎÎÎÎB7ÎÎÎÎB6 ÎÎÎÎB5 ÎÎ B4 ÎÎB3 ÎÎBÎÎ2 ÎÎBÎÎ1 ÎÎBÎÎ0 ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎC7ÎÎÎÎ}
MSB
LSB
EOC
Initialize
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
t(conv)
A/D Conversion
Interval
Initialize
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input signals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 11. Timing for 8-Clock Transfer Using CS With MSB First
CS
(see Note A)
I/O CLOCK
1
2
3
4
5
6
7
8
1
Access Cycle B
Sample Cycle B
DATA OUT
A7
A6
A5
A4
A3
A2
A1
A0
Previous Conversion Data
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _DATAINPUT
MSB
LSB
B7
B6
B5
B4
B3
B2
B1
B0
MSB
LSB
Low Level
B7
ÎÎÎÎ_CÎÎ₇ ÎÎ
EOC
Initialize
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
t(conv)
A/D Conversion
Interval
Initialize
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input signals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 12. Timing for 8-Clock Transfer Not Using CS With MSB First
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