TLC2543CDWR Datasheet, PDF (6/34 Pages) Texas Instruments – 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS

TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001
operating characteristics over recommended operating free-air temperature range,
V_CC = V_ref+ = 4.5 V to 5.5 V, f_{(I/O CLOCK)} = 4.1 MHz
PARAMETER
TEST CONDITIONS MIN TYP^†
MAX
UNIT
EL
Linearity error (see Note 5)
ED
Differential linearity error
EO
Offset error (see Note 6)
See Figure 2
See Figure 2
See Note 2 and
Figure 2
±1
LSB
±1
LSB
± 1.5
LSB
EG
Gain error (see Note 6)
See Note 2 and
Figure 2
±1
LSB
ET
Total unadjusted error (see Note 7)
DATA INPUT = 1011
± 1.75
LSB
2048
Self-test output code (see Table 3 and Note 8)
DATA INPUT = 1100
0
DATA INPUT = 1101
4095
t(conv)
tc
tacq
Conversion time
Total cycle time (access, sample, and conversion)
Channel acquisition time (sample)
See Figures 9 – 14
See Figures 9 – 14
and Note 9
See Figures 9 – 14
and Note 9
8
10
µs
10 + total
I/O CLOCK
periods +
µs
td(I/O-EOC)
I/O
4
12 CLOCK
periods
tv
td(I/O-DATA)
td(I/O-EOC)
td(EOC-DATA)
tPZH, tPZL
tPHZ, tPLZ
tr(EOC)
tf(EOC)
tr(bus)
tf(bus)
td(I/O-CS)
Valid time, DATA OUT remains valid after I/O CLOCK↓
Delay time, I/O CLOCK↓ to DATA OUT valid
Delay time, last I/O CLOCK↓ to EOC↓
Delay time, EOC↑ to DATA OUT (MSB / LSB)
Enable time, CS↓ to DATA OUT (MSB / LSB driven)
Disable time, CS↑ to DATA OUT (high impedance)
Rise time, EOC
Fall time, EOC
Rise time, data bus
Fall time, data bus
Delay time, last I/O CLOCK↓ to CS↓ to abort conversion
(see Note 10)
See Figure 6
See Figure 6
See Figure 7
See Figure 8
See Figure 3
See Figure 3
See Figure 8
See Figure 7
See Figure 6
See Figure 6
10
ns
150
ns
1.5
2.2
µs
100
ns
0.7
1.3
µs
70
150
ns
15
50
ns
15
50
ns
15
50
ns
15
50
ns
5
µs
† _{All typical values are at TA = 25°C.}
NOTES: 2. Analog input voltages greater than that applied to REF + convert as all ones (111111111111), while input voltages less than that
applied to REF – convert as all zeros (000000000000).
5. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
6. Gain error is the difference between the actual midstep value and the nominal midstep value in the transfer diagram at the specified
gain point after the offset error has been adjusted to zero. Offset error is the difference between the actual midstep value and the
nominal midstep value at the offset point.
7. Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
8. Both the input address and the output codes are expressed in positive logic.
9. I/O CLOCK period = 1 /(I/O CLOCK frequency) (see Figure 7).
10. Any transitions of CS are recognized as valid only when the level is maintained for a setup time. CS must be taken low at ≤ 5 µs
of the tenth I/O CLOCK falling edge to ensure a conversion is aborted. Between 5 µs and 10 µs, the result is uncertain as to whether
the conversion is aborted or the conversion results are valid.
6
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