THS7347 Datasheet, PDF (9/28 Pages) Texas Instruments – 3-Channel RGBHV Video Buffer with I2C™ Control, 2:1 Input Mux, Monitor Pass-Through, and Selectable Input Bias Modes

THS7347
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TIMING REQUIREMENTS FOR I²C INTERFACE⁽¹⁾⁽²⁾
At V_DD = 2.7 V to 5 V.
f_SCL
t_w(H)
t_w(L)
t_r
t_f
t_su(1)
t_h(1)
t_(buf)
t_su(2)
t_h(2)
t_su(3)
C_b
PARAMETER
Clock frequency, SCL
Pulse duration, SCL high
Pulse duration, SCL low
Rise time, SCL and SDA
Fall time, SCL and SDA
Setup time, SDA to SCL
Hold time, SCL to SDA
Bus free time between stop and start conditions
Setup time, SCL to start condition
Hold time, start condition to SCL
Setup time, SCL to stop condition
Capacitive load for each bus line
STANDARD MODE
MIN
MAX
0
100
4
4.7
1000
300
250
0
4.7
4.7
4
4
400
SLOS531 – MAY 2007
FAST MODE
MIN
MAX
0
400
0.6
1.3
300
300
100
0
1.3
0.6
0.6
0.6
400
UNIT
kHz
µs
µs
ns
ns
ns
ns
µs
µs
µs
µs
pF
(1) The THS7347 I²C address = 01011(A1)(A0)(R/W). See the Applications Information section for more information.
(2) The THS7347 was designed to comply with version 2.1 of the I²C specification.
SCL
t _w(H)
t _w(L)
t_r
t_f
t _su(1)
t _h(1)
SDA
Figure 1. SCL and SDA Timing
SCL
SDA
t _su(2)
t _h(2)
t _su(3)
t _(buf)
Start Condition
Stop Condition
Figure 2. Start and Stop Conditions
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