THS7347 Datasheet, PDF (17/28 Pages) Texas Instruments – 3-Channel RGBHV Video Buffer with I2C™ Control, 2:1 Input Mux, Monitor Pass-Through, and Selectable Input Bias Modes

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APPLICATIONS INFORMATION (continued)
SDA
SCL
Data Line
Stable;
Data Valid
Change of Data Allowed
Figure 6. I²C Bit Transfer
THS7347
SLOS531 – MAY 2007
Data Output
by Transmitter
Data Output
by Receiver
Not Acknowledge
Acknowledge
SCL From
Master
1
2
8
9
S
Start
Condition
Figure 7. I²C Acknowledge
Clock Pulse for
Acknowledgement
• The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from
the slave (R/W bit 0). In either case, the receiver must acknowledge the data sent by the transmitter. So, an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long
as necessary (see Figure 8).
12 3 4 5 6 78 9 123 4 5 67 8 9
SCL
SDA
MSB
Acknowledge
Slave Address
Data
Stop
Acknowledge
Figure 8. I²C Address and Data Cycles
• To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low
to high while the SCL line is high (see Figure 5). This transaction releases the bus and stops the
communication link with the addressed slave. All I²C-compatible devices must recognize the stop condition.
Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start
condition followed by a matching address.
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