THS7347 Datasheet, PDF (21/28 Pages) Texas Instruments – 3-Channel RGBHV Video Buffer with I2C™ Control, 2:1 Input Mux, Monitor Pass-Through, and Selectable Input Bias Modes

THS7347
www.ti.com
SLOS531 – MAY 2007
Table 4. THS7347 Channel Register (H/V Sync Channel + Analog Channels State) Bit Decoder Table.
Use in Conjunction With Register Bit Code (0000 0100)
BIT
(MSB)
7
6
5
4, 3
2, 1
0
(LSB)
FUNCTION
BIT
VALUE(S)
RESULT
Reserved; Do not care
X
Reserved; do not care
Monitor Pass-Through Path Disable
Mode
(Use in Conjunction with Table 3)
0
Disables all monitor channels regardless of bits 2:0 of Register 1
through Register 3
1
Enables monitor channels functions dictated by each programmed
register code
Buffer Path Disable Mode
(Use in Conjunction with Table 3)
0
Disables all buffer channels regardless of bits 2:0 of Register 1
through Register 3
1
Enables buffer channel functions dictated by each programmed
register code
00
MUX Input A
Vertical Sync Channel MUX Selection
01
MUX Input B
10
Reserved; do not care
11
Reserved; do not care
00
MUX Input A
01
MUX Input B
Horizontal Sync Channel MUX Selection
10
Reserved; do not care
11
Reserved; do not care
H/V Sync Paths Disable Mode
0
Disable H-Sync and V-Sync Channels
1
Enable H-Sync and V-Sync Channels
Bit (MSB) 7: Reserved; do not care.
Bit 6: Master Monitor Path Disable. Disables all monitor channels regardless of what is programmed into
each register channel (1 to 3).
Bit 5: Master Buffer Path Disable. Disables all buffer channels regardless of what is programmed into each
register channel (1 to 3).
Bits 4, 3: Selects the Input MUX channel for the Vertical Sync.
Bits 2, 1: Selects the Input MUX channel for the Horizontal Sync.
Bit 0 (LSB): Enables or disables the H-Sync and V-Sync Channels.
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