THS7347 Datasheet, PDF (16/28 Pages) Texas Instruments – 3-Channel RGBHV Video Buffer with I2C™ Control, 2:1 Input Mux, Monitor Pass-Through, and Selectable Input Bias Modes

THS7347
SLOS531 – MAY 2007
www.ti.com
APPLICATIONS INFORMATION (continued)
I²C INTERFACE NOTES
The I²C interface is used to access the internal registers of the THS7347. I²C is a two-wire serial interface
developed by Philips Semiconductor (see the I2C Bus Specification, Version 2.1, January 2000). The THS7347
was designed in compliance with version 2.1 specifications. The bus consists of a data line (SDA) and a clock
line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the
I²C-compatible devices connect to the I²C bus through open-drain I/O pins, SDA and SCL. A master device,
usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating
the SCL signal and device addresses. The master also generates specific conditions that indicate the START
and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master
device. The THS7347 works as a slave and supports the standard mode transfer (100 kbps) and fast mode
transfer (400 kbps) as defined in the I²C Bus Specification. The THS7347 has been tested to be fully functional
with the high-speed mode (3.4 Mbps) but it is not specified at this time.
Figure 5 shows the basic I²C start and stop access cycles.
The basic access cycle consists of the following:
• A start condition
• A slave address cycle
• Any number of data cycles
• A stop condition
SDA
SCL
S
Start
Condition
Figure 5. I²C Start and Stop Conditions
P
Stop
Condition
GENERAL I²C PROTOCOL
• The master initiates data transfer by generating a start condition. The start condition exists when a
high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 5. All I²C-compatible
devices should recognize a start condition.
• The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit
R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition
requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 6). All devices
recognize the address sent by the master and compare it to the respective internal fixed addresses. Only the
slave device with a matching address generates an acknowledge (see Figure 7) by pulling the SDA line low
during the entire high period of the ninth SCL cycle. On detecting this acknowledge, the master knows that a
communication link with a slave has been established.
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