THS1240 Datasheet, PDF (9/20 Pages) Texas Instruments – 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER

THS1240
12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS279D – JUNE 2000 – REVISED JANUARY 2001
APPLICATION INFORMATION
using the THS1240 clock input (continued)
If the dc component of the input clock differs from V_DD/2 by more than 10%, it is best to connect the CLK+ input
to the clock source through a 0.01 µF capacitor. In this mode, the converter can operate with a clock having a
peak-to-peak voltage of as little as 2 V with little or no performance degradation (see Figure 9).
Square Wave or
Sine Wave
2 V p-p to 5 V p-p
0.01 µF
CLK+
THS1240
CLK–
0.01 µF
Figure 9. AC-Coupled Single-Ended Clock Input
The THS1240 clock input can also be driven differentially. If the common mode of the clock input is V_DD/2, then
the clock inputs can be driven directly (see Figure 10)
Differential Square Wave or
Sine Wave 2 V p-p to 5 V p-p
Common Mode Voltage = VDD/2
CLK+
THS1240
CLK–
Figure 10. Differential Clock Input
If the clock input is driven differentially with a clock signal having a common mode voltage that is different from
V_DD/2, then it is best to connect both clock inputs to the differential input clock signal with 0.01 µF capacitors
(see Figure 11). The differential input swing can vary between 2 V and 5 V with little or no performance
degradation.
Differential Square Wave or
Sine Wave
2 V p-p to 5 V p-p
0.01 µF
CLK+
THS1240
0.01 µF
CLK–
Figure 11. AC-Coupled Differential Clock Input
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