THS1240 Datasheet, PDF (2/20 Pages) Texas Instruments – 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER

THS1240
12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS279D – JUNE 2000 – REVISED JANUARY 2001
functional block diagram
VIN+
1 kΩ
VIN–
VREFIN+
VREFOUT+
VREFOUT–
VREFIN–
VCM
CLK+
CLK–
AVDD DVDD DRVDD
Buffer
S/H
A/D
3.0 V
2
Reference
2.0 V ^AVDD/2
Stage 1
Σ
D/A
Stages 2 – 9
Stage 10
Stage 11
Σ ^A/D
A/D D/A
1
1
Digital Error Correction
Timing
AVSS DVSS DRVSS D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Terminal Functions
TERMINAL
I/O
NAME
NO.
DESCRIPTION
AVDD
2, 5, 12, 43, I Analog power supply
45, 47
AVSS
1, 11, 13, 41, I Analog ground return for internal analog circuitry
42, 44, 46
CLK+
15
I Clock input
CLK–
16
I Complementary clock input
D11–D0
25–36
O Digital data output bits; LSB= D0, MSB = D11 (2s complement output format)
DRVDD
DRVSS
DVDD
DVSS
VBG
VCM
VIN+
VIN_–
VREFIN _–
VREFIN+
VREFOUT+
VREFOUT _–
24, 37, 38
23, 39, 40
17, 20, 22
18, 19, 21
10
48
3
4
7
8
9
6
I Digital output driver supply
I Digital output driver ground return
I Positive digital supply
I Digital ground return
O Band gap reference. Bypass to ground with a 1-µF and a 0.01-µF chip capacitor.
O Common mode voltage output. Bypass to ground with a 0.1-µF and a 0.01-µF chip capacitor.
I Analog signal input
I Complementary analog signal input
I External reference input low
I External reference input high
O Internal reference output. Compensate with a 1-µF and a 0.01-µF chip capacitor.
O Internal reference output. Compensate with a 1-µF and a 0.01-µF chip capacitor.
2
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