THS1240 Datasheet, PDF (5/20 Pages) Texas Instruments – 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER

THS1240
12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS279D – JUNE 2000 – REVISED JANUARY 2001
ac specifications over recommended operating free-air temperature range, AV_DD = DV_DD = 5 V,
DRV_DD = 3.3 V, internal references, CLK = 40 MHz, analog input at –2 dBFS, single-ended clock
source at 40 MHz with 50% duty cycle (unless otherwise noted)
SNR
PARAMETER
Signal-to-noise ratio
SINAD
Signal-to-noise and distortion
ENOB
THD
Effective number of bits
Total harmonic distortion
SFDR
Spurious-free dynamic range
2nd Harmonic Distortion
3rd Harmonic Distortion
Two tone SFDR
† _{All typical values are at TA = 25°C.}
TEST CONDITIONS
fIN = 2.2 MHz
fIN = 15.5 MHz
fIN = 15.5 MHz, V(IN) = –0.5 dBFS
fIN = 31 MHz
fIN = 70 MHz
fIN = 2.2 MHz
fIN = 15.5 MHz
fIN = 15.5 MHz, V(IN) = –0.5 dBFS
fIN = 31 MHz
fIN = 70 MHz
fIN = 15.5 MHz
fIN = 15.5 MHz, V(IN) = –0.5 dBFS
fIN = 15.5 MHz
fIN = 15.5 MHz, V(IN) = –0.5 dBFS
fIN = 2.2 MHz
fIN = 15.5 MHz
fIN = 15.5 MHz, V(IN) = –0.5 dBFS
fIN = 31 MHz
fIN = 70 MHz
fIN = 2.2 MHz
fIN = 15.5 MHz
fIN = 31 MHz
fIN = 70 MHz
fIN = 2.2 MHz
fIN = 15.5 MHz
fIN = 31 MHz
fIN = 70 MHz
F1 = 14.9 MHz, F2 = 15.6 MHz,
Analog inputs at – 8 dBFS each
MIN TYP^†
64.6
64
63 65.5
64
64
63.3
64
62 64.5
63.2
55.7
10.2
10 10.4
–72
–71
73
70
77
72
77
59.6
82
–87
–77
–60.5
–73
–80.4
–77
–60
MAX
–68
–70
–70
UNIT
dB
dB
bits
dBc
dBc
dBc
dBc
72
dBc
operating characteristics over recommended operating conditions, AV_DD = DV_DD = 5 V,
DRV_DD = 3.3 V
switching specifications
PARAMETER
Aperture delay, td(A)
Aperture jitter
Output delay td(O), after falling edge of CLK+
Pipeline delay td(PIPE)
† _{All typical values are at TA = 25°C.}
TEST CONDITIONS
Digital outputs driving a 15 pF load each
MIN TYP^†
120
1
6.5
MAX UNIT
ps
ps RMS
13 ns
CLK
Cycle
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