THS1240 Datasheet, PDF (3/20 Pages) Texas Instruments – 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER

THS1240
12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS279D – JUNE 2000 – REVISED JANUARY 2001
functional description
The THS1240 uses a differential pipeline architecture and assures no missing codes over the full operating
temperature range. The device uses a 1 bit per stage architecture in order to achieve the highest possible
bandwidth. The differential analog inputs are terminated with a 1-kΩ resistor. The inputs are then fed to a unity
gain buffer followed by the S/H (sample and hold) stage. This S/H stage is a switched capacitor operational
amplifier-based circuit, see Figure 3. The pipeline is a typical 1 bit per stage pipeline as shown in the functional
block diagram. The digital output of the 12 stages is sent to a digital correction logic block which then outputs
the final 12 bits.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)^†
Supply voltage range: AV_DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
DV_DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
DRV_DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Voltage between AV_SS and DV_SS and DRV_SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 0.5 V
Voltage between DRV_DD and DV_DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 5 V
Voltage between AV_DD and DV_DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 5 V
Digital data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to DV_DD + 0.3 V
CLK peak input current, I_p(CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Peak total input current (all inputs), I_p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30 mA
Operating free-air temperature range, T_A: THS1240C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
THS1240I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† _{Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and}
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
Sample rate
Analog supply voltage, AVDD
Digital supply voltage, DVDD
Digital output driver supply voltage, DRVDD
CLK + high level input voltage, VIH^‡
CLK + low-level input voltage, VIL^‡
CLK pulse-width high, tp(H)
CLK pulse-width low, tp(L)
Operating free-air temperature range, TA
THS1240C
THS1240I
‡ _{CLK– Input tied to ground with 0.01 µF capacitor for single-ended clock source.}
MIN NOM MAX UNIT
1
40 MSPS
4.75
5 5.25 V
4.75
5 5.25 V
3 3.3 5.25 V
3.5
5 5.25 V
0
1.5 V
10 12.5
ns
10 12.5
ns
0
70
°C
– 40
85
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