TCA9554A Datasheet, PDF (9/33 Pages) Texas Instruments – LOW VOLTAGE 8-BIT I2C AND SMBus I/O EXPANDER

TCA9554A
www.ti.com
SCPS196 – DECEMBER 2010
Register Descriptions
The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is
defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these
registers have no effect. The default value, X, is determined by the externally applied logic level.
Before a read operation, a write transmission is sent with the command byte to let the I²C device know that the
Input Port register will be accessed next.
BIT
DEFAULT
Table 5. Register 0 (Input Port Register)
I7
I6
I5
I4
I3
I2
I1
I0
X
X
X
X
X
X
X
X
The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the
Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
BIT
DEFAULT
Table 6. Register 1 (Output Port Register)
O7
O6
O5
O4
O3
O2
O1
O0
1
1
1
1
1
1
1
1
The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration
register. If a bit in this register is set (written with 1), the corresponding port pin polarity is inverted. If a bit in this
register is cleared (written with a 0), the corresponding port pin original polarity is retained.
Table 7. Register 2 (Polarity Inversion Register)
BIT
DEFAULT
N7
N6
N5
N4
N3
N2
N1
N0
0
0
0
0
0
0
0
0
The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1,
the corresponding port pin is enabled as an input with high impedance output driver. If a bit in this register is
cleared to 0, the corresponding port pin is enabled as an output.
BIT
DEFAULT
Table 8. Register 3 (Configuration Register)
C7
C6
C5
C4
C3
C2
C1
C0
1
1
1
1
1
1
1
1
Power-On Reset
When power (from 0 V) is applied to V_CC, an internal power-on reset holds the TCA9554A in a reset condition
until V_CC has reached V_POR. At that point, the reset condition is released and the TCA9554A registers and
I²C/SMBus state machine will initialize to their default states. After that, V_CC must be lowered to below 0.2 V and
then back up to the operating voltage for a power-reset cycle.
ADD TABLE WITH SPECS AND DEFINITIONS TO SUPPORT POR OPERATION
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