TCA9554A Datasheet, PDF (10/33 Pages) Texas Instruments – LOW VOLTAGE 8-BIT I2C AND SMBus I/O EXPANDER

TCA9554A
SCPS196 – DECEMBER 2010
www.ti.com
Interrupt Output (INT)
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, t_iv, the
signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original
setting; data is read from the port that generated the interrupt. Resetting occurs in the read mode at the
acknowledge (ACK) bit or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that
occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt
during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the
state of the pin does not match the contents of the Input Port register.
INT has an open-drain structure and requires a pullup resistor to V_CC.
Bus Transactions
Data is exchanged between the master and TCA9554A through write and read commands.
Writes
Data is transmitted to the TCA9554A by sending the device address and setting the least-significant bit to a logic
0 (see Figure 4 for device address). The command byte is sent after the address and determines which register
receives the data that follows the command byte (see Figure 6 and Figure 7). There is no limitation on the
number of data bytes sent in one write transmission.
SCL
12 345 678 9
Slave Address
Command Byte
Data to Port
SDA S 0 1 1 1 A2 A1 A0 0 A 0 0 0 0 0 0 0 1 A
Data 1
Start Condition
Write to Port
R/W ACK From Slave
ACK From Slave
AP
ACK From Slave
Data Out
From Port
Figure 6. Write to Output Port Register
Data 1 Valid
t_pv
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SCL 1 2 3 4 5 6 7 8 9
Slave Address
Command Byte
Data to Register
SDA _{S 0 1 1 1 A2 A1 A0 0 A 0 0 0 0 0 0 1 1/0 A}
Data
Start Condition
R/W ACK From Slave
ACK From Slave
Data to
Register
Figure 7. Write to Configuration or Polarity Inversion Registers
AP
ACK From Slave
10
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