TCA9554A Datasheet, PDF (11/33 Pages) Texas Instruments – LOW VOLTAGE 8-BIT I2C AND SMBus I/O EXPANDER

TCA9554A
www.ti.com
SCPS196 – DECEMBER 2010
Reads
The bus master first must send the TCA9554A address with the least significant bit (LSB) set to a logic 0 (see
Figure 4 for device address). The command byte is sent after the address and determines which register is
accessed. After a restart, the device address is sent again, but this time the LSB is set to a logic 1. Data from the
register defined by the command byte then is sent by the TCA9554A (see Figure 8 and Figure 9). After a restart,
the value of the register defined by the command byte matches the register being accessed when the restart
occurred. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the
number of data bytes received in one read transmission, but when the final byte is received, the bus master must
not acknowledge the data.
Slave Address
ACK From
Slave
ACK From
Slave
Slave Address
ACK From
ACK From
Slave ^{Data From Register Master}
S 0 1 1 1 A2 A1 A0 0 A
R/W
Command Byte
A S 0 1 1 1 A2 A1 A0 1 A
R/W
Data
A
<br/>
SCL
SDA
Read From
Port
Data Into
Port
Figure 8. Read From Register
NACK From
Data From Register _Master
Data
Last Byte
NA P
12 345678 9
Slave Address
Data From Port
S 0 1 1 1 A2 A1 A0 1 A
Data 1
Start
Condition
R/W
ACK From
Slave
Data From Port
A
Data 4
NA P
ACK From
Master
NACK From
Master
Stop
Condition
Data 2
Data 3
t_ph
t_ps
Data 4
Data 5
INT
t_iv
t_ir
A. This figure assumes the command byte has previously been programmed with 00h.
B. Transfer of data can be stopped at any moment by a Stop condition.
C. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from the P port. See Figure 8 for these details.
Figure 9. Read From Input Port Register
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TCA9554A
Submit Documentation Feedback
11