TCA9554A Datasheet, PDF (5/33 Pages) Texas Instruments – LOW VOLTAGE 8-BIT I2C AND SMBus I/O EXPANDER

TCA9554A
www.ti.com
SCPS196 – DECEMBER 2010
Data From
Shift Register
Data From
Shift Register
Write Configuration
Pulse
Write Pulse
Read Pulse
SIMPLIFIED SCHEMATIC OF P0 TO P7
Configuration
Register
DQ
FF
C_K Q
Q1
DQ
FF
C_K Q
Output Port
Register
Input Port
Register
DQ
FF
C_K Q
100 kW
Q2
Data From
Shift Register
Write Polarity
Pulse
DQ
FF
C_K Q
Polarity
Inversion
Register
Output Port
Register Data
V_CC
P0 to P7
GND
Input Port
Register Data
INT
Polarity
Register Data
A. At power-on reset, all registers return to default values.
I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high impedance input with a
weak pullup (100 kΩ typ) to V_CC. The input voltage may be raised above V_CC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In
this case, there are low impedance paths between the I/O pin and either V_CC or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
I²C Interface
The bidirectional I²C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I²C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 1). After the Start condition, the device address byte
is sent, most significant bit (MSB) first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. The address inputs (A0–A2) of the slave device must
not be changed between the Start and Stop conditions.
On the I²C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (Start or Stop) (see Figure 2).
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