DS90C365AMTX Datasheet, PDF (9/16 Pages) Texas Instruments – +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display Link-87.5 MHz

DS90C365A
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SNLS181I – APRIL 2004 – REVISED APRIL 2013
these cases should then be asserted once a stable clock is applied to the LVDS transmitter. Asserting the PWR
DOWN pin will effectively place the device in reset and disable the PLL, enabling the LVDS Transmitter into a
power saving standby mode. However, it is still generally a good practice to assert the PWR DOWN pin or reset
the LVDS transmitter whenever the clock/data is stopped and reapplied but it is not mandatory for the
DS90C365A.
SPREAD SPECTRUM CLOCK SUPPORT
The DS90C365A can support Spread Spectrum Clocking signal type inputs. The DS90C365A outputs will
accurately track Spread Spectrum Clock/Data inputs with modulation frequencies of up to 100kHz (max.)with
either center spread of ±2.5% or down spread -5% deviations.
POWER SOURCES SEQUENCE
In typical applications, it is recommended to have V_CC, LVDS V_CC and PLL V_CC from the same power source with
three separate de-coupling bypass capacitor groups. There is no requirement on which VCC entering the device
first.
Pin Diagram for TSSOP Package
Top View
Figure 13. Order Number DS90C365AMT
DGG0048A Package
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