DS90C365AMTX Datasheet, PDF (8/16 Pages) Texas Instruments – +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display Link-87.5 MHz

DS90C365A
SNLS181I – APRIL 2004 – REVISED APRIL 2013
PIN DESCRIPTIONS
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DS90C365A DGG0048A (TSSOP) Package Pin Descriptions — FPD Link Transmitter
Pin Name
I/O
No.
Description
TxIN
I
21 LVTTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3control lines—FPLINE, FPFRAME
and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
TxOUT+
O
3 Positive LVDS differentiaI data output.
TxOUT−
O
3 Negative LVDS differential data output.
TxCLKIN
I
1 LVTTL Ievel clock input. Pin name TxCLK IN.
R_FB
I
1 LVTTL Ievel programmable strobe select (See Table 1).
TxCLK OUT+
O
1 Positive LVDS differential clock output.
TxCLK OUT−
O
1 Negative LVDS differential clock output.
PWR DOWN
I
1 LVTTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at
power down.
V_CC
GND
I
3 Power supply pins for LVTTL inputs.
I
5 Ground pins for LVTTL inputs.
PLL V_CC
PLL GND
I
1 Power supply pin for PLL.
I
2 Ground pins for PLL.
LVDS V_CC
LVDS GND
I
1 Power supply pin for LVDS outputs.
I
3 Ground pins for LVDS outputs.
NC
1 No connect
APPLICATIONS INFORMATION
The DS90C365A is backward compatible with the DS90C365, DS90C363A, DS90C363 in TSSOP 48-lead
package, and it is a pin-for-pin replacements.
This device DS90C365A also features reduced variation of the TCCD parameter which is important for dual pixel
applications. See AN-1084(SNLA001)
This device may also be used as a replacement for the DS90CF563 (5V, 65MHz) and DS90CF561 (5V, 40MHz)
FPD-Link Transmitters with certain considerations/modifications:
1. Change 5V power supply to 3.3V. Provide this 3.3V supply to the V_CC, LVDS V_CC and PLL V_CC of the
transmitter.
2. The DS90C365A transmitter input and control inputs accept 3.3V LVTTL/LVCMOS levels. They are not 5V
tolerant.
3. To implement a falling edge device for the DS90C365A, the R_FB pin may be tied to ground OR left
unconnected (an internal pull-down resistor biases this pin low). Biasing this pin to Vcc implements a rising
edge device.
TRANSMITTER INPUT PINS
The TxIN and control input pins are compatible with LVCMOS and LVTTL levels. These pins are not 5V tolerant.
TRANSMITTER INPUT CLOCK/DATA SEQUENCING
Unlike the DS90C365, DS90C(F)383A/363A, the DS90C365A does not require any special requirement for
sequencing of the input clock/data and PD (PowerDown) signal. The DS90C365A offers a more robust input
sequencing feature where the input clock/data can be inserted after the release of the PD signal. In the case
where the clock/data is stopped and reapplied, such as changing video mode within Graphics Controller, it is not
necessary to cycle the PD signal. However, there are in certain cases where the PD may need to be asserted
during these mode changes. In cases where the source (Graphics Source) may be supplying an unstable clock
or spurious noisy clock output to the LVDS transmitter, the LVDS Transmitter may attempt to lock onto this
unstable clock signal but is unable to do so due the instability or quality of the clock source. The PD signal in
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