DS90C365AMTX Datasheet, PDF (4/16 Pages) Texas Instruments – +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display Link-87.5 MHz

DS90C365A
SNLS181I – APRIL 2004 – REVISED APRIL 2013
Transmitter Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
TPPos0
Parameter
Transmitter Output Pulse Position (Figure 12)⁽¹⁾ f = 40 MHz
Min
Typ
−0.25
0
TPPos1
Transmitter Output Pulse Position
3.32
3.57
TPPos2
Transmitter Output Pulse Position
6.89
7.14
TPPos3
Transmitter Output Pulse Position
10.46
10.71
TPPos4
Transmitter Output Pulse Position
14.04
14.29
TPPos5
Transmitter Output Pulse Position
17.61
17.86
TPPos6
TPPos0
Transmitter Output Pulse Position
Transmitter Output Pulse Position (Figure 12)⁽¹⁾ f = 65 MHz
21.18
−0.20
21.43
0
TPPos1
Transmitter Output Pulse Position
2.00
2.20
TPPos2
Transmitter Output Pulse Position for Bit 2
4.20
4.40
TPPos3
Transmitter Output Pulse Position for Bit 3
6.39
6.59
TPPos4
Transmitter Output Pulse Position
8.59
8.79
TPPos5
Transmitter Output Pulse Position
10.79
10.99
TPPos6
TPPos0
Transmitter Output Pulse Position
Transmitter Output Pulse Position (Figure 12)⁽¹⁾ f = 87.5 MHz
12.99
−0.20
13.19
0
TPPos1
Transmitter Output Pulse Position
1.48
1.68
TPPos2
Transmitter Output Pulse Position
3.16
3.36
TPPos3
Transmitter Output Pulse Position
4.84
5.04
TPPos4
Transmitter Output Pulse Position
6.52
6.72
TPPos5
Transmitter Output Pulse Position
8.20
8.40
TPPos6
Transmitter Output Pulse Position
9.88
10.08
TSTC
Required TxIN Setup to TxCLK IN
2.5
(Figure 6) at 85MHz
THTC
Required TxIN Hold to TxCLK IN (Figure 6) at
0.5
87.5 MHz
TCCD
TxCLK IN to TxCLK OUT Delay. Measure from
TxCLK IN edge to immediatley crossing poing
of differential TxCLK OUT by following the
postive TxCLK OUT. 50% duty cycle input
clock is assumed. (Figure 7)
T_A = −10°C, and
85MHz for "Min" T_A
= 70°C, and
25MHz for "Max",
V_CC = 3.6V, R_FB
pin = VCC
3.086
Measure from TxCLK IN edge to immediatley
crossing poing of differential TxCLK OUT by
following the postive TxCLK OUT. 50% duty
cycle input clock is assumed. (Figure 8)
T_A = −10°C, and
85MHz for "Min" T_A
= 70°C, and
25MHz for "Max",
V_CC = 3.6V, R_FB
pin = GND
2.868
SSCG
Spread Spectrum Clock support; Modulation
frequency with a linear profile.⁽²⁾
f = 25 MHz
100kHz ±
2.5%/−5%
f = 40 MHz
100kHz ±
2.5%/−5%
f = 65 MHz
100kHz ±
2.5%/−5%
f = 87.5 MHz
100kHz ±
2.5%/−5%
TPLLS
Transmitter Phase Lock Loop Set (Figure 9)
TPDD
Transmitter Power Down Delay (Figure 11)
Max
+0.25
3.82
7.39
10.96
14.54
18.11
21.68
+0.20
2.40
4.60
6.79
8.99
11.19
13.39
+0.20
1.88
3.56
5.24
6.92
8.60
10.28
7.211
6.062
10
100
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Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
(2) Care must be taken to ensure TSTC and THTC are met so input data are sampling correctly. This SSCG parameter only shows the
performance of tracking Spread Spectrum Clock applied to TxCLK IN pin, and reflects the result on TxCLKOUT+ and TxCLKOUT− pins.
4
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