BQ4013 Datasheet, PDF (9/14 Pages) Texas Instruments – 128Kx8 Nonvolatile SRAM

bq4013/Y
Power-Down/Power-Up Cycle (TA = TOPR)
Symbol
Parameter
Minimum
tPF
VCC slew, 4.75 to 4.25 V
300
tFS
VCC slew, 4.25 to VSO
10
tPU
VCC slew, VSO to VPFD (max.)
0
tCER
Chip enable recovery time
40
tDR
Data-retention time in
absence of V_CC
10
tDR-N
Data-retention time in
absence of V_CC
6
tWPT
Write-protect time
40
Typical
-
-
-
80
-
-
100
Maximum
-
-
-
120
Unit
µs
µs
µs
ms
Conditions
Time during which
SRAM is
write-protected after
VCC passes VPFD on
power-up.
-
years TA = 25°C. (2)
-
years
TA = 25°C (2); industrial
temperature range only
Delay after VCC slews
150
µs
down past VPFD before
SRAM is
write-protected.
Notes: 1. Typical values indicate operation at TA = 25°C, VCC = 5V.
2. Battery is disconnected from circuit until after VCC is applied for the first time. tDR is the
accumulated time in absence of power beginning when power is first applied to the device.
Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode
may affect data integrity.
Power-Down/Power-Up Timing
9