BQ4013 Datasheet, PDF (7/14 Pages) Texas Instruments – 128Kx8 Nonvolatile SRAM

bq4013/Y
Write Cycle (TA =TOPR _{, VCCmin} ≤ VCC ≤ VCCmax)
Symbol
Parameter
-70/-70N -85/-85N
-120
Units
Min. Max. Min. Max. Min. Max.
Conditions/Notes
tWC
Write cycle time
70 - 85 - 120 -
ns
tCW
Chip enable to end of
write
65 - 75 - 100 -
ns
(1)
tAW
Address valid to end of
write
65
-
75
- 100 -
ns
(1)
tAS
Address setup time
0
-
0
-0-
ns
Measured from address valid
to beginning of write. (2)
tWP
Write pulse width
55 - 65 - 85 -
ns
Measured from beginning of
write to end of write. (1)
tWR1
Write recovery time
(write cycle 1)
5
-
5
-5-
ns
Measured from WE going high
to end of write cycle. (3)
tWR2
Write recovery time
(write cycle 2)
15 - 15 - 15 -
ns
Measured from CE going high
to end of write cycle. (3)
tDW
Data valid to end of
write
30 - 35 - 45 -
ns
Measured to first low-to-high
transition of either CE or WE.
tDH1
Data hold time
(write cycle 1)
0
-
0
-0-
ns
Measured from WE going high
to end of write cycle. (4)
tDH2
Data hold time
(write cycle 2)
10 - 10 - 10 -
ns
Measured from CE going high
to end of write cycle. (4)
tWZ
Write enabled to output
in high Z
0
25
0
30
0
40
ns I/O pins are in output state. (5)
tOW
Output active from end
of write
0
-
0
-
0
-
ns I/O pins are in output state. (5)
Notes:
1. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition
of CE going low and WE going low.
3. Either tWR1 or tWR2 must be met.
4. Either tDH1 or tDH2 must be met.
5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.
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