BQ25120_15 Datasheet, PDF (9/68 Pages) Texas Instruments – bq25120 700-nA Low IQ Highly Integrated Battery Charge Management Solution for Wearables and IoT

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BQ25120
SLUSBZ9A – AUGUST 2015 – REVISED AUGUST 2015
Electrical Characteristics (continued)
Circuit of , V_(UVLO) < V_IN < V_(OCP) and V_IN > V_(BAT) + V_(SLP), T_J = -40 to 85°C and T_J = 25°C for typical values (unless otherwise
noted)
PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
K_(ISET)
Fast Charge Current Factor 5 mA > I_(CHARGE) > 300 mA
190
200
210
AΩ
Termination charge current
Termination current programmable range over
I²C
0.5
37
mA
I_(TERM)
Termination Current using
IPRETERM
Accuracy
I_(CHARGE) < 300 mA, R_(ITERM) = 15 kΩ
I_(CHARGE) < 300 mA, R_(ITERM) = 4.99 kΩ
I_(CHARGE) < 300 mA, R_(ITERM) = 1.65 kΩ
I_(CHARGE) < 300 mA, R_(ITERM) = 549 Ω
5
% of I_SET
10
% of I_SET
15
% of I_SET
20
% of I_SET
-10%
10%
t_DGL(TERM)
TERM deglitch time
Both rising and falling, 2-mV over-drive, t_RISE,
t_FALL = 100 ns
64
ms
Pre-charge current
Pre-charge current programmable range over
I²C
0.5
37
mA
I_{(PRE_CHARGE)}
Pre-charge Current using
I_PRETERM
Accuracy
I_(TERM)
A
-10%
10%
V_(RCH)
t_DGL(RCHG)
Recharge threshold voltage
Recharge threshold deglitch
time
Below V_(BATREG)
t_FALL = 100 ns typ, V_(RCH) falling
100
120
140
mV
32
ms
SYS OUTPUT
R_{DS(ON_HS)}
R_{DS(ON_LS)}
R_{DS(CH_SYS)}
MOSFET on-resistance for
SYS discharge
PMID = 3.6 V, I_(SYS) = 50 mA
PMID = 3.6 V, I_(SYS) = 50 mA
V_IN = 3.6 V, I_OUT = -10 mA into V_OUT pin
675
850
mΩ
300
475
mΩ
22
40
Ω
I_(LIMF)
I_O
I_{(LIM_SS)}
SW Current limit HS
SW Current limit LS
DC Output Current
PMOS switch current limit
during softstart
2.2V < V_(PMID) < 5.5 V
2.2V < V_(PMID) < 5.5 V
Current limit is reduced during softstart
525
600
675
mA
525
700
850
mA
200
300
mA
80
130
200
mA
SYS Output Voltage Range Programmable range, 100 mV Steps
1.1
3.3
V
V_SYS
Output Voltage Accuracy
DC Output Voltage Load
Regulation in PWM mode
V_IN = 5 V, PFM mode, I_OUT = 10 mA, V_(SYS) =
1.8 V
V_OUT = 2 V, Load range
-2.5%
0
0.01
2.5%
%/mA
DC Output Voltage Line
Regulation in PWM mode
V_OUT = 2.V, I_OUT = 100 mA, VIN RANGE
0.01
%/V
LS/LDO OUTPUT
V_IN(LS)
Input voltage range for
LS/LDO
Input voltage range for
LS/LDO
Load Switch Mode
LDO Mode
0.8
6.6
V
2.2
6.6
V
V_OUT
DC output accuracy
T_J = 25°C
Over V_IN, I_OUT, temperature
-2%
±1%
2%
-3%
±2%
3%
V_LDO
Output range for LS/LDO
Programmable Range, 0.1 V steps
0.8
3.3
V
DC Line regulation
ΔV_OUT / Δ V_{IN DC Load regulation}
V_OUT(NOM) + 0.5 V < V_IN < 6.6 V, I_OUT = 5 mA
-1%
0 mA < I_OUT < 100 mA
-1%
1%
1%
Load Transient
2 uA to 100 mA, VOUT = 1. 8V
-120
60
mV
R_{DS(ON_LDO)}
R_{(DSCH_LSLDO)}
FET Rdson
MOSFET on-resistance for
LS/LDO discharge
V_(VINLS) = 3.6 V
1.7V < V_(VINLS) < 6.6 V, I_LOAD = -10 mA
460
600
mΩ
30
Ω
I_{(OCL_LDO)}
I_(LS/LDO)
Output Current Limit – LDO
Output Current
V_LS/LDO = 0.9 x V_LS/LDO(NOM)
V_(VINLS) = 3.6 V, V_LSLDO = 3.3 V
V_(VINLS) = 3.3 V, V_LSLDO = 0.8 V
V_(VINLS) = 2.2 V, V_LSLDO = 0.8 V
275
365
450
mA
100
mA
100
mA
10
mA
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