BQ25120_15 Datasheet, PDF (20/68 Pages) Texas Instruments – bq25120 700-nA Low IQ Highly Integrated Battery Charge Management Solution for Wearables and IoT

BQ25120
SLUSBZ9A – AUGUST 2015 – REVISED AUGUST 2015
www.ti.com
9.3.5 Sleep Mode
The device enters the low-power sleep mode if the voltage IN falls below the sleep-mode entry threshold and V_IN
is higher than the undervoltage lockout threshold. In sleep mode, the input is isolated from the battery. This
feature prevents draining the battery during the absence of V_IN. When V_IN < V_(BAT) + V_SLP, the device turns the
battery discharge FET on, sends a 128-µs pulse on the INT output, and the FAULT bits of the register are update
over I²C. Once V_IN > V_(BAT) + V_SLP, the device initiates a new charge cycle. The FAULT bits are not cleared until
they are read over I²C and the sleep condition no longer exists.
9.3.6 Input Voltage Based Dynamic Power Management (V_IN(DPM))
During the normal charging process, if the input power source is not able to support the programmed or default
charging current and System load, the supply voltage decreases. Once the supply drops to V_IN(DPM), the input
DPM current and voltage loops will reduce the input current through the blocking FETs, to prevent the further
drop of the supply. The V_IN(DPM) threshold is programmable through the I²C register from 4.2 V to 4.9 V in 100-
mV steps. It can be disabled completely as well. When the device enters this mode, the charge current may be
lower than the set value and the VINDPM_STAT bit is set. If the 2X timer is set, the safety timer is extended
while V_IN(DPM) is active. Additionally, termination is disabled.
9.3.7 Input Overvoltage Protection and Undervoltage Status Indication
The input overvoltage protection protects the device and downstream components connected to PMID, SYS, and
BAT against damage from overvoltage on the input supply. When V_IN > V_OVP, after the deglitch time, t_{DGL_OVP}, an
OVP fault is determined to exist. During the OVP fault, the device turns the battery discharge FET on, sends a
single 128-µs pulse on INT, and the FAULT bits are updated over I²C. Once the OVP fault is removed, STAT
and FAULT bits are cleared and the device returns to normal operation. The FAULT bits are not cleared until
they are read in from I²C after the OVP condition no longer exists. The OVP threshold for the device is set to
operate from standard USB sources.
The input under-voltage status indication is used to notify the host or other device when the input voltage falls
below a desired threshold. When V_IN < V_UVLO, after the deglitch time t_{DGL_UVLO}, a UVLO fault is determined to
exist. During the V_IN UVLO fault, the device sends a single 128-µs pulse on INT, and the STAT and FAULT bits
are updated over I²C. The FAULT bits are not cleared until they are read in from I²C after the UVLO condition no
longer exists.
9.3.8 Battery Charging Process and Charge Profile
When a valid input source is connected (V_IN > V_UVLO and V_(BAT) + V_SLP < V_IN < V_OVP), the CE bit in the control
register determines whether a charge cycle is initiated. When the CE bit is 1 and a valid input source is
connected, the battery discharge FET is turned off, and the output at SYS is regulated depending on the output
configuration. A charge cycle is initiated when the CE bit is written to a 0. Alternatively, the CD input can be used
to enable and disable charge.
The device supports multiple battery chemistries for single-cell applications. Charging is done through the
internal battery MOSFET. There are several loops that influence the charge current: constant current loop (CC),
constant voltage loop (CV), input current limit, V_DPPM, and V_IN(DPM). During the charging process, all loops are
enabled and the one that is dominant takes control.
The charge current is regulated to I_CHARGE until the voltage between BAT and GND reaches the regulation
voltage. The voltage between BAT and GND is regulated to V_BATREG (CV Mode) while the charge current
naturally tapers down. When termination is enabled, the device monitors the charging current during the CV
mode, and once the charge current tapers down to the termination threshold, I_TERM, and the battery voltage is
above the recharge threshold, the device terminates charge, and turns off the battery charging FET. Termination
is disabled when any loop is active other than CV.
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