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BQ20Z45 Datasheet, PDF (9/20 Pages) Texas Instruments – SBS 1.1-Compliant Gas Gauge and Protection Enabled With Impedance Track™
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bq20z45
www.ti.com .................................................................................................................................................................................................. SLUS800 – MARCH 2009
DATA FLASH CHARACTERISTICS OVER RECOMMENDED OPERATING TEMPERATURE AND
SUPPLY VOLTAGE
Typical Values at TA = 25°C and V(REG25) = 2.5 V (unless otherwise noted)
PARAMETER
Data retention
Flash programming write-cycles
t(ROWPROG) Row programming time
t(MASSERASE) Mass-erase time
t(PAGEERASE) Page-erase time
I(DDPROG) Flash-write supply current
I(DDERASE) Flash-erase supply current
RAM BACKUP
I(RB)
V(RB)
RB data-retention input current
RB data-retention input voltage(1)
See (1)
TEST CONDITIONS
V(RBI) > V(RBI)MIN , VREG25 < VIT–, TA = 85°C
V(RBI) > V(RBI)MIN , VREG25 < VIT–, TA = 25°C
MIN TYP MAX
10
20k
2
200
20
5 10
5 10
UNIT
Years
Cycles
ms
ms
ms
mA
mA
1000 2500
nA
90 220
1.7
V
(1) Specified by design. Not production tested.
SMBus TIMING CHARACTERISTICS
TA = –40°C to 85°C Typical Values at TA = 25°C and VREG25 = 2.5 V (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
f(SMB)
f(MAS)
SMBus operating frequency
SMBus master clock frequency
Slave mode, SMBC 50% duty cycle
Master mode, No clock low slave
extend
10
100 kHz
51.2
kHz
t(BUF)
Bus free time between start and stop
(see Figure 1)
4.7
µs
t(HD:STA)
t(SU:STA)
t(SU:STO)
t(HD:DAT)
Hold time after (repeated) start (see Figure 1)
Repeated start setup time (see Figure 1)
Stop setup time (see Figure 1)
Data hold time (see Figure 1)
Receive mode
Transmit mode
4
µs
4.7
µs
4
µs
0
ns
300
t(SU:DAT)
t(TIMEOUT)
t(LOW)
t(HIGH)
t(LOW:SEXT)
t(LOW:MEXT)
Data setup time (see Figure 1)
Error signal/detect (see Figure 1)
Clock low period (see Figure 1)
Clock high period (see Figure 1)
Cumulative clock low slave extend time
Cumulative clock low master extend time
(see Figure 1)
tf
Clock/data fall time
tr
Clock/data rise time
See (1)
See (2)
See (3)
See (4)
See (5)
See (6)
250
ns
25
35 µs
4.7
µs
4
50 µs
25 ms
10 ms
300 ns
1000 ns
(1) The bq8040 times out when any clock low exceeds t(TIMEOUT).
(2) t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving bq8040 that is in
progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0).
(3) t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(4) t(LOW:MEXT) is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
(5) Rise time tr = VILMAX – 0.15) to (VIHMIN + 0.15)
(6) Fall time tf = 0.9VDD to (VILMAX – 0.15)
Copyright © 2009, Texas Instruments Incorporated
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